Patents by Inventor Takema Ito

Takema Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7847270
    Abstract: According to the present invention, there is provided a semiconductor manufacturing apparatus having: a process flow information creating section which registers an exposure device as a device for performing the pattern writing processing and an electron beam direct writing device as an alternative to the exposure device, when creating process flow information by sequentially registering processing conditions of processings in a semiconductor manufacturing process; and a control section which searches for information on the pattern writing processing based on the process flow information before the pattern writing processing, determines whether or not a mask used by the exposure device for performing the pattern writing processing searched for is installed in the exposure device, and sets the exposure device to perform the pattern writing processing in the case where it has been determined that the mask is installed in the exposure device, or sets the electron beam direct writing device to perform the patt
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takema Ito, Hiroyuki Morinaga, Arata Inoue
  • Patent number: 7512501
    Abstract: A defect inspecting apparatus comprising: an inspection region dividing section which divides a defect inspection region of a wafer on which a circuit pattern is formed into a plurality of inspection subregions; a pattern density calculating section which calculates the pattern density of each of the inspection subregions on the basis of design data of the circuit pattern; an inspection execution region and sensitivity rank setting section which assigns a sensitivity rank based on the pattern density to a plurality of inspection execution regions, each including a plurality of the inspection subregions; and a defect inspecting section which sets an inspection parameter on the basis of sensitivity ranks of the inspection execution regions and inspects the inspection execution regions for a defect.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: March 31, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Morinaga, Atsushi Onishi, Masayoshi Yamasaki, Takema Ito, Yasuhiro Kaga
  • Publication number: 20080052021
    Abstract: A defect inspecting apparatus comprising: an inspection region dividing section which divides a defect inspection region of a wafer on which a circuit pattern is formed into a plurality of inspection subregions; a pattern density calculating section which calculates the pattern density of each of the inspection subregions on the basis of design data of the circuit pattern; an inspection execution region and sensitivity rank setting section which assigns a sensitivity rank based on the pattern density to a plurality of inspection execution regions, each including a plurality of the inspection subregions; and a defect inspecting section which sets an inspection parameter on the basis of sensitivity ranks of the inspection execution regions and inspects the inspection execution regions for a defect.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 28, 2008
    Inventors: Hiroyuki Morinaga, Atsushi Onishi, Masayoshi Yamasaki, Takema Ito, Yasuhiro Kaga
  • Patent number: 7260443
    Abstract: A system for making a recipe for each of manufacturing tools used to manufacture products includes a merging unit merging product information for the products and process information for each of manufacturing processes used for the products to make intermediate recipe data, and a making unit making the recipe for each of the manufacturing tools by merging information of the intermediate recipe data and information of a basic recipe including information of parameters, which specify operations of the manufacturing tools and are commonly set in the manufacturing processes.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Morinaga, Takema Ito, Arata Inoue, Takuya Kono, Takashi Sakamoto
  • Patent number: 7239934
    Abstract: A design system for delivering data via a network to a plant, which fabricates a semiconductor device by direct writing, includes: a data conversion unit generating the data specified by a product name of the semiconductor device, a layer name, and a machine type of an electron beam lithography system for the direct writing; a central memory unit recording the data; and a plant mediator distributing the data to the plant via the network, and re-distributing the data to the plant in response to a download request associated with the product name, the layer name, and the machine type.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Morinaga, Takema Ito
  • Publication number: 20060287752
    Abstract: According to the present invention, there is provided a semiconductor manufacturing apparatus having: a process flow information creating section which registers an exposure device as a device for performing the pattern writing processing and an electron beam direct writing device as an alternative to the exposure device, when creating process flow information by sequentially registering processing conditions of processings in a semiconductor manufacturing process; and a control section which searches for information on the pattern writing processing based on the process flow information before the pattern writing processing, determines whether or not a mask used by the exposure device for performing the pattern writing processing searched for is installed in the exposure device, and sets the exposure device to perform the pattern writing processing in the case where it has been determined that the mask is installed in the exposure device, or sets the electron beam direct writing device to perform the pattern
    Type: Application
    Filed: April 27, 2006
    Publication date: December 21, 2006
    Inventors: Takema Ito, Hiroyuki Morinaga, Arata Inoue
  • Publication number: 20060051687
    Abstract: An inspection system includes a microscope configured to observe a mask pattern of a photomask and a projected image of the mask pattern on a substrate, a circuit data memory configured to store design data of a circuit pattern to be formed on the substrate by the mask pattern, a file generator configured to generate a coordinate file regarding the design data, the observed mask pattern, and the observed projected image, and an image interface configured to display same coordinates of the design data, the observed mask pattern, and the observed projected image based on the coordinates file.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 9, 2006
    Inventors: Takema Ito, Hiroyuki Morinaga
  • Publication number: 20060020362
    Abstract: A system for making a recipe for each of manufacturing tools used to manufacture products includes a merging unit merging product information for the products and process information for each of manufacturing processes used for the products to make intermediate recipe data, and a making unit making the recipe for each of the manufacturing tools by merging information of the intermediate recipe data and information of a basic recipe including information of parameters, which specify operations of the manufacturing tools and are commonly set in the manufacturing processes.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 26, 2006
    Inventors: Hiroyuki Morinaga, Takema Ito, Arata Inoue, Takuya Kono, Takashi Sakamoto
  • Publication number: 20050177268
    Abstract: A design system for delivering data via a network to a plant, which fabricates a semiconductor device by direct writing, includes: a data conversion unit generating the data specified by a product name of the semiconductor device, a layer name, and a machine type of an electron beam lithography system for the direct writing; a central memory unit recording the data; and a plant mediator distributing the data to the plant via the network, and re-distributing the data to the plant in response to a download request associated with the product name, the layer name, and the machine type.
    Type: Application
    Filed: July 29, 2004
    Publication date: August 11, 2005
    Inventors: Hiroyuki Morinaga, Takema Ito