Abstract: Timing of internally generated horizontal synchronization signal and vertical synchronization signal is shifted. An internal clock is synchronized with a horizontal synchronization signal separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon. A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18. Here, the VS output circuit 18 internally has a delay circuit, and the timing of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS.

Abstract: Timing of internally generated horizontal synchronization signal and vertical synchronization signal is shifted. An internal clock is synchronized with a horizontal synchronization signal separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon. A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18. Here, the VS output circuit 18 internally has a delay circuit, and the timing of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS.

Abstract: There has been no appropriate means to test connections between two integrated circuits packaged in a single semiconductor package.

Abstract: A white balance adjusting apparatus includes a test signal source 13 for generating a black signal for testing and a white signal for testing, a first impedance means 1 for converting currents flowing through three drive transistors for amplifying primary color R, G, B signals into voltages, a second impedance means 5 connected in parallel with the first impedance means, a switch 6 which is selectively closed to flow a current through the second impedance means, a reference voltage source 7 for generating a first reference voltage at the time of performing the cut-off adjustment and a second reference voltage at the time of performing the drive adjustment, a comparator 8 for comparing the levels between the reference voltages of the reference voltage sources and the output voltage converted by the first or second impedance means, and a microcomputer 75 which generates a control signal for adjusting the white balance on the basis of the output signal of the comparator and adjusts the DC level and the AC level

Abstract: There has been no appropriate means to test connections between two integrated circuits packaged in a single semiconductor package.

Abstract: A saw-wave generator (51) creates a saw-wave. Two comparators (COMP1, C0MP2) obtain two control signals having different duty ratios. Using these two control signals, two transistors (54, 56) are switched ON and OFF in complement and at voltage boost output when transistor (54) is OFF and transistor (56) is ON, transistor (57) is switched from ON to OFF and transistor (59) is switched from ON to OFF. A quadrupled voltage is thereby obtained.

Abstract: A television synchronous deflection circuit is generally comprised of a first power supply for supplying a D.C. voltage to a horizontal AFC circuit in the horizontal deflector of a television receiver, a second power supply for smoothing the flyback pulse and for supplying a predetermined D.C. voltage to a synchronous separator, and a comparator for comparing the output voltages of the first and second power supply circuits with each other. According to a comparison signal outputted from the comparator, the operation of the horizontal AFC circuit is controlled. For example, when the output voltage of the second power supply is less than a predetermined value, operation of the horizontal AFC circuit is prohibited; and when it is larger than the predetermined value, such prohibition is released.