Patents by Inventor Takemi Negishi
Takemi Negishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7443212Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: GrantFiled: August 9, 2007Date of Patent: October 28, 2008Assignee: Renesas Technology Corp.Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Publication number: 20080211548Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: April 29, 2008Publication date: September 4, 2008Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Publication number: 20070296470Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: August 9, 2007Publication date: December 27, 2007Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Publication number: 20070236844Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: ApplicationFiled: June 6, 2007Publication date: October 11, 2007Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 7262643Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: GrantFiled: July 17, 2006Date of Patent: August 28, 2007Assignee: Renesas Technology Corp.Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Patent number: 7233045Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: GrantFiled: October 12, 2004Date of Patent: June 19, 2007Assignee: Hitachi LtdInventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 7176729Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: GrantFiled: April 22, 2004Date of Patent: February 13, 2007Assignee: Renesas Technology Corp.Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Publication number: 20060255842Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: July 17, 2006Publication date: November 16, 2006Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Publication number: 20050063112Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: ApplicationFiled: October 12, 2004Publication date: March 24, 2005Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 6835971Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.Type: GrantFiled: January 31, 2003Date of Patent: December 28, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Toyoshima, Atsuhiro Hayashi, Takemi Negishi, Takashi Uehara
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Publication number: 20040251940Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.Type: ApplicationFiled: April 22, 2004Publication date: December 16, 2004Inventors: Atsuhiro Hayashi, Takemi Negishi, Hiroshi Toyoshima
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Patent number: 6806516Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: GrantFiled: February 21, 2003Date of Patent: October 19, 2004Assignee: Renesas Technology Corp.Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Publication number: 20030222285Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: ApplicationFiled: February 21, 2003Publication date: December 4, 2003Applicant: Hitachi, Ltd.Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Publication number: 20030151100Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.Type: ApplicationFiled: January 31, 2003Publication date: August 14, 2003Applicant: Hitachi, Ltd.Inventors: Hiroshi Toyoshima, Atsuhiro Hayashi, Takemi Negishi, Takashi Uehara