Patents by Inventor Takenori Okada

Takenori Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976020
    Abstract: A method for producing a (meth)acrylic acid amide compound, the method including: adding at least one selected from the group consisting of an amino group-containing compound and a neutralization salt of the amino group-containing compound to a mixture including (meth)acrylic acid halide and an organic solvent immiscible with water to allow the (meth)acrylic acid halide and at least one selected from the group consisting of the amino group-containing compound and the neutralization salt of the amino group-containing compound to react with each other, to produce the (meth)acrylic acid amide compound.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: May 7, 2024
    Assignee: RICOH COMPANY, LTD.
    Inventors: Mitsunobu Morita, Masahide Kobayashi, Takenori Suenaga, Soh Noguchi, Takashi Okada
  • Patent number: 6370098
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Patent number: 6348883
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: February 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Publication number: 20010038593
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Application
    Filed: February 21, 2001
    Publication date: November 8, 2001
    Applicant: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Publication number: 20010030614
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Application
    Filed: February 21, 2001
    Publication date: October 18, 2001
    Applicant: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Patent number: 6233213
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: May 15, 2001
    Assignee: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio