Abstract: A magnetism measuring device includes a light source unit, a diamond crystal and an image sensor. The light source unit irradiates the diamond crystal with an excitation light, and irradiates the image sensor with a fluorescent light generated by the diamond crystal. The diamond crystal includes a plurality of nitrogen-vacancy pairs. The image sensor detects an intensity of the fluorescent light, which is generated from the diamond crystal, by a plurality of pixels. The image sensor and the light source unit are disposed so as to be contained within a projection area of the diamond crystal.

Abstract: A magnetism measuring device includes a light source unit, a diamond crystal and an image sensor. The light source unit irradiates the diamond crystal with an excitation light, and irradiates the image sensor with a fluorescent light generated by the diamond crystal. The diamond crystal includes a plurality of nitrogen-vacancy pairs. The image sensor detects an intensity of the fluorescent light, which is generated from the diamond crystal, by a plurality of pixels. The image sensor and the light source unit are disposed so as to be contained within a projection area of the diamond crystal.

Abstract: A semiconductor integrated circuit with a IP test circuit having a IP test circuit, a IP6, a IP7, a COU 4, a SRAM 5. The IP test circuit has a IP test controller 21 including a register 21, a test sequencer 2, a selector 3, and a bus interface 11. Under the control of the IP test controller 1, a test program and test data in serial form are transferred from an external tester through a test data terminal 9 and then converted to the test program and the test data in parallel form. The converted test program and the test data are stored into the SRAM 5. The CPU 4 executes the test operation for the IP6 directly connected to a cpu bus 8. The test sequencer 7 executes the test operation for the IP7 that is not directly connected to the cpu bus 8. The test results are transferred to the external tester through the test data terminal.

Abstract: A shield interconnection layer 8 is disposed on a third insulating film 6c in such a manner as to cover the entire surface of a region in which a functional cell 3 is formed. The shield interconnection layer 8 is connected through a second through-hole 10 to an interconnection layer having a specific potential such as a power supply interconnection layer or a ground interconnection layer in a region different from the region in which the functional cell 3 is formed.

Abstract: A BIST circuit built in a LSI device incorporating a LSI memory such as a DRAM, a SRAM, a Flash memory, and the like has a repair code generator/register (7) and a selector (6) or a self repair circuit (8). The repair code generator/register (7) generates a repair code regarding information of a redundancy memory cell to be used instead of a faulty memory cell when a comparator (3) indicates that a memory cell array (51) includes the faulty memory cell. The selector (6) selectively outputs data stored in the GO/NG register (4) and the repair code generator/register (7). The self repair circuit (8) repairs the faulty memory cell based on the repair code.

Abstract: A semiconductor device in which outputs of flip-flops are not stopped even if one of the logic blocks of a test circuit is not activated. A burn-in test circuit has an XOR circuit by which, when an output signal and a burn-in input signal of one logic block is supplied, the other logic blocks are activated.

Abstract: An image data storing device capable of solving a problem involved in a conventional device in that an increasing number of memory bus lines are required which are used for simultaneously reading pixel data from memory elements as the dimension of a screen increases, and that this hinders the device from being integrated. The present image data storing device includes n (a positive integer) physical banks, to which memory buses are connected in one to one correspondence with them. Each physical bank stores image data with their rows and columns different from each other.

Abstract: A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively to an incoming basic clock signal. A plurality of storage elements store therein a predetermined level in response to transitions occurring in associated ones of the basic and delayed clock signals after an asynchronous trigger signal is applied thereto. A clock selection logic circuit is controlled by the output signal from the storage elements for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of the clock signals based on the result of the detection, as a synchronized clock input signal.

Abstract: A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively relative to an incoming basic clock signal. Storage means includes a plurality of storage elements storing therein a predetermined level in response to transitions occurring in associated ones of said basic and delayed clock signals after a trigger signal which is asynchronous with the basic clock signal is applied thereto. A clock selection logic circuit is controlled by the output signal of the storage means for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of said clock signals, based on the result of the detection, as a synchronized clock signal output.

Abstract: A plurality of first word lines are connected to a first word selector, and a plurality of second word lines are connected to a second word selector. A plurality of first bit lines are connected to a first bit selector, and a plurality of second bit lines are connected to a second bit selector. Each memory cell includes two inverters and first and second access gates. Each memory cell is connected to the first word line, the second word line, the first bit line and the second bit line. In data writing, data is written to a node through the first access gate. In data reading, data at the node or node is read through either the first or the second access gate.

Abstract: Address pointers (11, 12, 13, 14) include flip-flop circuits and flip-flop circuits including data through circuits. A control circuit (10) controls the flip-flop circuits such that the data through circuits of unnecessary flip-flop circuits cause data to pass through to prevent the flip-flop circuits from selecting unnecessary memory cells (7). The control circuit (10) generates control signals in selection signal producing means including fuses and the like and a decoding portion. Since the decoding portion decodes a flip-flop selection signal, the number of fuses is reduced. This achieves a semiconductor memory comprising address parts for memory cell selection and redundancy circuits which has a reduced area for provision of the fuses for providing redundancy to the semiconductor memory.

Abstract: Disclosed is the serial access memory having the improved precharging system of reading bit lines (4). In this serial access memory, an address pointer (9, 114) outputs a signal for selecting one of the reading bit lines (4). Meanwhile, each reading bit line (4) is provided with an MOS transistor (7) for precharging the same. By using the output of the address pointer (9, 114) to control on/off of the MOS transistor (7), the period when each reading bit line (4) is precharged is limited within the period when the reading bit line is selected. As a result, current flowing through the reading bit lines (4) during the data reading can be reduced to achieve the reduction in power consumption of the serial access memory and the increase in the operation speed.

Abstract: A LIFO device includes a plurality of memory circuits (1), a write address pointer (2) and a read-out address pointer (3). The write address pointer (2) selects the memory circuit (1) in which data are to be written, while the read-out address pointer (3) selects the memory circuit (1) from which data are to be read out. Each of the write address pointer (2) and the read-out address pointer (3) alternately and repeatedly performs the count-up operation for selecting the memory circuits in a predetermined sequence and the count-down operation of selecting the memory circuits in a sequence which is the reverse of the predetermined sequence. Control is also so made that the selection by the read-out address pointer (3) precedes the selection by the write address pointer (2).

Abstract: In a driver circuit, two P-channel MOS transistors are connected in parallel between a supply terminal and an output terminal, and two P-channel MOS transistors are connected in parallel between a ground terminal and the output terminal. When a signal of the "H" level is applied to an input terminal, a signal of the "L" level is applied sequentially to these transistors. As a result, the N-channel MOS transistors are sequentially turned off, and thereafter the P-channel MOS transistors are sequentially turned on. When a signal of the "L" level is applied to the input terminal, a signal of the "H" level is applied sequentially to these transistors. As a result, the P-channel MOS transistors are sequentially turned off, and thereafter the N-channel MOS transistors are sequentially turned on.

Abstract: A dynamic RAM includes a memory cell comprised of a data read transistor, a data write transistor and a data storage capacitor. The data write transistor is turned on in response to a row selection signal to connect the capacitor to a write bit line. The dynamic RAM includes a structure for shifting the level of potential of internal write data to be transmitted onto the write bit line. This structure will prevent the data write transistor from being turned on by the undershoot produced on the write bit line.

Abstract: An NPN type bipolar transistor is connected between a first connection terminal for power supply voltage and an output terminal and its base is connected to an output of an inverter as a first internal circuit. An N channel MOS transistor is connected between the output terminal and a second connection terminal for ground potential and its gate is connected to an output of a second internal circuit. On the other hand, another N channel MOS transistor is connected between an input terminal and the second connection terminal and its gate is connected to the second connection terminal. An inverter as a third internal circuit is connected between the input terminal and the second internal circuit. The first and second connection terminals are connected to each of the first, second and third internal circuits. The second internal circuit is further connected with a state control terminal for controlling an output of the output terminal.

Abstract: An input protecting device of a semiconductor circuit device has a first power supply terminal (8) for providing a first supply potential, a second power supply terminal (9) for providing a second supply potential, a signal input terminal (1), a first clamping diode (3) provided between the first power supply terminal (8) and the signal input terminal (1) for clamping a voltage larger than the first supply potential applied to the signal input terminal (1), and a second clamping diode (4) provided between the second power supply terminal (9) and the signal input terminal (1) for clamping a voltage smaller than the second supply potential applied to the signal input terminal (1). A switching device (12, 20 or 33) selectively cuts off a current path between the first clamping diode (3) and the signal input terminal (1) when a voltage is not applied to the first power supply terminal (8).

Abstract: An interconnection circuit of a semiconductor integrated circuit connected between a first circuit (41) for applying an input signal and the second circuit (44) for outputting an output signal to the other circuit comprises circuits of input stage, processing stage and output stage. The circuit of the input stage comprises an n channel MOS field effect transistor (14) and a resistance (7). The circuit of the processing stage comprises two CMOS inverters (1, 2, 31, 32). The circuit of the output stage comprises a CMOS inverter (15, 16) and a series connection of a resistance (21), an npn bipolar transistor (17) and an n channel MOS filed effect transistor (18). When an overvoltage is applied to the input terminal (8), the circuit of the input stage protects the circuit by a parasitic diode (25) formed by the transistor (14) or the punch through phenomenon of the transistor (14). When the power supply V.sub.

Abstract: A three-state complementary field effect integrated circuit comprises an output pre-stage circuit (11) connected to an input terminal (1) and a first and second control input (6, 5) and comprising a series connection of a first switching circuit (9), a second switching circuit (7, 8) having resistances (P5, N5) and a third switching means (10); an output circuit (12) comprising a series connection of a p type and an n type field effect transistors (P1, N1) with capacitors (C1, C2) connected between respective gates and the ground (GND). When the voltages of H and L level are applied to the first and second control input (6, 5), the resistance (P5, N5) comprised in the second switching means and the capacitors (C1, C2) connected to the gates of the transistors constitute integrating circuits. When the output voltage changes, the transistors (P1, N1) are prevented from simultaneously turning on, whereby a through current flowing into the output circuit is prevented.

Abstract: A complemenary MOS integrated circuit comprising an output circuit and a pre-output circuit, which is capable of reducing a penetration current which occurs upon switching of transistors in the output circuit, to thereby suppress an occurrence of spike noises in an output signal. The pre-output circuit comprises MOS transistors constituting an analog switch, "on-resistances" of which are utilized as a resistor, and MOS transistor gates. A series circuit of the analog switch and the gates are coupled in series with a power source.