Abstract: A semiconductor device includes: a through-electrode formed in a perpendicular direction so as to extend therethrough; a series circuit section formed from a plurality of test-ready switches successively connected in series and driven by a driving voltage transmitted to the through-electrode through a predetermined different layer through-electrode of a different semiconductor device stacked on an upper layer side or a lower layer side; and a pair of test terminals connected to end portions of the series circuit section and adapted to be used for measurement of conduction of the series circuit section.

Abstract: A semiconductor device includes: a through-electrode formed in a perpendicular direction so as to extend therethrough; a series circuit section formed from a plurality of test-ready switches successively connected in series and driven by a driving voltage transmitted to the through-electrode through a predetermined different layer through-electrode of a different semiconductor device stacked on an upper layer side or a lower layer side; and a pair of test terminals connected to end portions of the series circuit section and adapted to be used for measurement of conduction of the series circuit section.

Abstract: A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in cascade. Data is sampled at the timing of the rising edge of the clock signal generated by a pulse generation circuit connected to a clock input circuit and data is output at the timing of the trailing edge. By defining the clock pulse width generated at the pulse generation circuit larger than the clock skew, it is possible to prevent malfunctions of the LSI caused by clock skew caused by deviation of timing of the clock distribution. Moreover, by providing a dynamic type through circuit for a scan test input to the first dynamic type through latch circuit in parallel, a scanning function can be realized and a malfunction due to the clock skew during scanning can be prevented.