Abstract: Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n+ drain region side, and a low resistance region positioned on a gate electrode side.

Abstract: Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n+ drain region side, and a low resistance region positioned on a gate electrode side.

Abstract: Propagation delay times of an input signal from an input terminal to respective gates are equalized and accelerated with a power MOS transistor that includes a plurality of transistor blocks. The transistor blocks are formed by sources being connected to each other by a first electric conductive layer (8.sub.2, 8.sub.4, 8.sub.6 and 10), drains being connected to each other by a second electric conductive layer (8.sub.1, 8.sub.3, 8.sub.5 and 9), and gates (6) consisting of a continuous semiconductor layer. The transistor has a third electric conductive layer (11) being connected to a gate terminal Gin and laminated on the gates. The third electric conductive layer laminated on the gates functions to equalize and accelerate propagation delay times of an input signal from an input terminal to the respective gates.