Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: An information processor having a control unit in which a plurality of instructions to simultaneously be executed are decoded by a decoder section, an executing unit to be dispatched of a plurality of executing units is selected by an index selecting section according to a result of the decoding, and dispatch to any of the plurality of executing units is inhibited by a dispatch inhibiting section according to a result of the decoding by the decoder section as well as to a result of the selection by the index selecting section.

Abstract: A general-purpose register address output from an instruction register is read and changed to a corresponding register update buffer address in an update table. Additionally, the update reservation instructing bit corresponding to the general-purpose register address is read out from a register update reservation table. If its value is "0", the general-purpose register address is provided to the general-purpose register, and the data stored at that address is input to an arithmetic unit. If the value of the bit is "1", the contents of the corresponding entry in the update table is registered to a reservation station. The reservation station determines the execution order of respective entries, and sequentially provides a register update buffer address to a register update buffer, and inputs the data stored at that address to the arithmetic unit.

Abstract: A polyphenylene sulfide resin composition improved in the impact strength, toughness, high temperature resistance and solvent resistance properties is disclosed. The composition comprises(A) 60-99.5% by weight of a thermally cured polyphenylene sulfide material having a melt viscosity of 500-30,000 poises and which has been derived, by thermally curing, from a polyphenylene sulfide having a melt viscosity of 400 poises of higher and containing 0.05-5 mol % of amino groups on the basis of the phenylene sulfide repeating units, and(B) 40-0.5% by weight of a modified polyethylene material comprising at least one polyethylene onto which at least one unsaturated carboxylic acid and/or derivative thereof is graft-copolymerized in a proportion of 0.1-10% by weight of the total weight of said modified polyethylene material.

Abstract: A pipeline operation control method and system in which, in the execution of successive first and second instructions, to avoid a pipeline disturbance, the second instruction is shifted from a calculating state to a special state as a final state that does not conflict with the final state of the first instruction when the first instruction has two or more calculating states immediately before the final state, and when the special state can be inserted as the final state of the second instruction and the calculating state of the second instruction is carried out within a single machine cycle, whereby the final state of the first instruction and the special state of the second instruction are carried out at the same time.

Abstract: A circuit for executing conditional branch instructions in a pipeline process comprises registers for retaining condition codes settled set or determined at different stages, respectively, registers for retaining pipeline tags identifying instructions at the respective stages and indicating the stage where the condition codes are settled or set by the instructions, and a branch controller for deciding whether the settlement of condition codes for conditional branch instructions existing at the respective stage has occured responsive to the tags in a plurality of stages, and for selecting the settled condition codes from among the condition codes stored in the registers and indicating whether a branch should be performed.