Patents by Inventor Takeo Ishibashi

Takeo Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8178983
    Abstract: It is an object of the present invention to provide a water repellant composition for a substrate to be exposed which inhibits the back side of a substrate to be exposed from being contaminated by an immersion liquid, can improve adhesion between a film to be processed and an organic film directly overlying that film to inhibit film peeling, and has excellent workability, a method for forming a resist pattern, an electronic device produced by the formation method, a treatment method for imparting water repellency to a substrate to be exposed, a water repellent set for a substrate to be exposed, and a treatment method for imparting water repellency to a substrate to be exposed using the same. A water repellent composition for a substrate to be exposed including at least an organosilicon compound represented by the following general formula (1) and a solvent is used.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: May 15, 2012
    Assignees: Renesas Electronics Corporation, Asahi Glass Company, Limited
    Inventors: Takeo Ishibashi, Miwako Ishibashi, legal representative, Mamoru Terai, Takuya Hagiwara, Osamu Yokokoji, Yoko Takebe
  • Patent number: 8092703
    Abstract: It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takeo Ishibashi, Kazumasa Yonekura, Masahiro Tadokoro, Kazunori Yoshikawa, Yoshiharu Ono
  • Publication number: 20110221077
    Abstract: It is an object of the present invention to provide a water repellant composition for a substrate to be exposed which inhibits the back side of a substrate to be exposed from being contaminated by an immersion liquid, can improve adhesion between a film to be processed and an organic film directly overlying that film to inhibit film peeling, and has excellent workability, a method for forming a resist pattern, an electronic device produced by the formation method, a treatment method for imparting water repellency to a substrate to be exposed, a water repellent set for a substrate to be exposed, and a treatment method for imparting water repellency to a substrate to be exposed using the same. A water repellent composition for a substrate to be exposed including at least an organosilicon compound represented by the following general formula (1) and a solvent is used.
    Type: Application
    Filed: February 20, 2009
    Publication date: September 15, 2011
    Inventors: Takeo Ishibashi, Miwako Ishibashi, Mamoru Terai, Takuya Hagiwara, Osamu Yokokoji, Yoko Takebe
  • Patent number: 8017305
    Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takeo Ishibashi, Takayuki Saito, Maya Itoh, Shuji Nakao
  • Patent number: 7935636
    Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: May 3, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takeo Ishibashi
  • Publication number: 20100203456
    Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi
  • Patent number: 7727709
    Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: June 1, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi
  • Publication number: 20100104983
    Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
    Type: Application
    Filed: January 5, 2010
    Publication date: April 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Takeo ISHIBASHI, Takayuki Saito, Maya Itoh, Shuji Nakao
  • Patent number: 7670756
    Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takeo Ishibashi, Takayuki Saito, Maya Itoh, Shuji Nakao
  • Publication number: 20100021703
    Abstract: A developing method for immersion lithography is provided, realizing a process that is simple and low-cost and enables high repellency sufficient to allow high-speed scanning. The developing method for immersion lithography improved by inexpensive material without introducing any new facility, a solution to be used in the developing method, and an electronic device formed by using the developing method are provided. The developing method for immersion lithography is a method of developing for immersion lithography of an electronic device with a resist containing a surface segregation agent and chemically-amplified resist, including the step of development with alkali immersion, characterized by the dissolving and removing step, conducted using a dissolving and removing solution that selectively dissolves and removes the surface segregation agent of the resist.
    Type: Application
    Filed: June 24, 2009
    Publication date: January 28, 2010
    Inventors: Mamoru Terai, Takuya Hagiwara, Takeo Ishibashi, Miwako Ishibashi
  • Publication number: 20090227046
    Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.
    Type: Application
    Filed: May 15, 2009
    Publication date: September 10, 2009
    Applicant: Renesas Technology Corp.
    Inventor: Takeo Ishibashi
  • Patent number: 7544619
    Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: June 9, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Takeo Ishibashi
  • Publication number: 20090075187
    Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
    Type: Application
    Filed: November 14, 2008
    Publication date: March 19, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Takeo Ishibashi, Takayuki Saito, Maya Itoh, Shuji Nakao
  • Publication number: 20090039519
    Abstract: A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located on one side of the pad pattern in one of the plural columns, the pad pattern is connected to the line pattern located on the other side of the pad pattern in another column of the plural columns, and the line pattern located on one side of the pad pattern includes an open-circuit portion in another column. Therefore, a semiconductor device in which an interconnection pattern including the fine line-and-space-shape line pattern and the pad pattern is accurately formed at low cost, a semiconductor device production method, and a photomask used to produce the semiconductor device can be provided.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 12, 2009
    Inventors: Takayuki Saito, Takeo Ishibashi, Itaru Kanai
  • Patent number: 7459265
    Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: December 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takeo Ishibashi, Takayuki Saito, Maya Itoh, Shuji Nakao
  • Publication number: 20080241489
    Abstract: A method of forming a resist pattern through liquid immersion exposure in which exposure is performed such that a liquid film is formed between a substrate for a semiconductor device on which a processed film is formed and an objective lens arranged above the substrate is provided, and the substrate treated with a water-repellent agent solution composed of at least a water-repellent agent and a solvent is exposed to light.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 2, 2008
    Inventors: Takeo Ishibashi, Mamoru Terai, Takuya Hagiwara, Atsumi Yamaguchi
  • Publication number: 20080194109
    Abstract: A method of fabricating a semiconductor device includes the steps of: depositing on a main surface of a semiconductor substrate a layer to be processed; depositing a base layer on the layer to be processed; depositing a first intermediate layer and then a second intermediate layer on the base layer; patterning the second intermediate layer while the base layer covers the layer to be processed; depositing a first mask pattern on the patterned second intermediate layer; patterning the second intermediate layer with the first mask pattern; patterning the first intermediate layer and the base layer with the patterned second intermediate layer to form a second mask pattern; and patterning the layer to be processed, with the second mask pattern.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 14, 2008
    Inventors: Takeo Ishibashi, Kazumasa Yonekura, Masaaki Shinohara, Mamoru Terai
  • Publication number: 20080044759
    Abstract: A fine pattern forming material comprising a water soluble resin of polyvinyl alcohol derivative, etc., a water soluble crosslinking agent of melamine derivative, urea derivative, etc., an amine compound, a nonionic surfactant and water or a solution of a mixture of water and water soluble organic solvent, the solution exhibiting a pH value of >7. This fine pattern forming material is applied on to resist pattern (3) to thereby form coating layer (4), and the coating layer (4) is heated and developed to thereby form crosslinked coating layer (5). The thickness of the crosslinked coating layer is increased by the use of a secondary amine compound and/or tertiary amine compound over that realized when no amine compound is added, while the thickness of the crosslinked coating layer is decreased by the use of a quaternary amine.
    Type: Application
    Filed: August 23, 2005
    Publication date: February 21, 2008
    Inventors: Takeo Ishibashi, Kiyohisa Takahashi, Yusuke Takano
  • Publication number: 20070287298
    Abstract: It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 13, 2007
    Inventors: Takeo Ishibashi, Kazumasa Yonekura, Masahiro Tadokoro, Kazunori Yoshikawa, Yoshiharu Ono
  • Publication number: 20070224546
    Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.
    Type: Application
    Filed: January 31, 2007
    Publication date: September 27, 2007
    Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi