Abstract: Provided is a test method including: placing, on a placement unit, a panel level package in which a plurality of unsingulated devices are formed in a matrix; bringing a plurality of contacts electrically connected to a plurality of terminals of a test circuit into contact with a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead-out wirings to an internal circuit of each device in each row of the plurality of devices, respectively; and testing, by the test circuit, each device in the each row electrically connected via the plurality of contacts.

Abstract: Provided is a test method including: placing, on a placement unit, a panel level package formed with a plurality of unsingulated devices; bringing at least one contact electrically connected to at least one terminal of a test circuit into contact with at least one terminal of at least one device of the plurality of devices, respectively, the terminal being exposed on a second surface on a side opposite to a first surface on the placement unit side in the panel level package; and testing, by the test circuit, the at least one device electrically connected via the at least one contact.

Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.

Abstract: A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.

Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.

Abstract: Data output from a semiconductor device under test and a reference clock output therefrom in synchronization with the data are sampled by slightly phased-apart multiphase strobe pulses. The phases of points of change of the output data and the reference clock are obtained from the sampled outputs, then the phase difference between them is measured, and a check is made to determine if the phase difference falls within a predetermined range, thereby evaluating the semiconductor device under test on a pass/fail basis.

Abstract: A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.

Abstract: A comparator circuit includes a window high impedance detector which detects any glitches or fails in the high impedance state of the device under test (DUT) within a specified time range. The comparator circuit includes a first analog comparator for receiving an output signal of the DUT and comparing the output signal with a high threshold voltage, a second analog comparator for receiving the output signal of the DUT and comparing the output signal with a low threshold voltage, and a window high impedance detector for detecting a deviation from a high impedance state of the DUT throughout a specified time range and for producing a fail signal when the deviation is detected.

Abstract: Data output from a semiconductor device under test and a reference clock output therefrom in synchronization with the data are sampled by slightly phased-apart multiphase strobe pulses. The phases of points of change of the output data and the reference clock are obtained from the sampled outputs, then the phase difference between them is measured, and a check is made to determine if the phase difference falls within a predetermined range, thereby evaluating the semiconductor device under test on a pass/fail basis.

Abstract: The present invention relates to a conveyer comprising: a pair of conveyer belts movable in the direction of transportation of an article by rollers; and a pair of article-supporting belts for supporting an article, the article-supporting belts being positioned between and interlocked with the conveyer belts, wherein upper portions of the conveyer belts are positioned above the article-supporting belts.

Abstract: By providing a mechanism for removing static electricity, even slight electric charge caused by natural electrification is removed before holding solder balls. A necessary number of solder balls are held securely. The solder balls attracted by vacuum suction are brought close to pads until the solder balls come in contact with flux surfaces of pads. While continuously holding the solder balls using vacuum suction, the solder balls are pressed against the pads. The solder balls are embedded in the flux having adherence power and held. In a solder ball mounting apparatus, therefore, solder balls can be mounted on pads of a substrate securely without using electrostatic force which is difficult to control.

Abstract: A strobe generator includes four strobe pulse generators generating original strobe pulses having the same frequency, respectively, and correspondingly, four logical comparator circuits, the number of which is identical to that of the strobe pulse generators. Further, a mode selection circuit is provided which can set any one of mode 1, mode 2 and mode 3. In mode 1, an output signal V from a level comparator is latched by a new high speed strobe signal having a frequency four times the frequency of the original strobe pulse, and the latched signals are sequentially compared with expected value data signals. In mode 2, an output signal V from the level comparator is latched by two new high speed strobe signals having a frequency two times the frequency of the original strobe pulse, and the latched signals are sequentially compared with the expected value data signals.

Abstract: There is provided a method of bonding inner leads of lead frames to electrodes of semiconductor chips, including the steps of (a) pictorially recognizing bonding sites of inner leads a semiconductor chip through wires for the certain number of lead frames among a plurality of lead frames and analyzing the bonding sites to obtain coordinate data numerically expressing the bonding sites, (b) calculating statistic about dispersion in the thus obtained coordinate data, (c) judging whether the thus calculated statistic is smaller or greater than a predetermined threshold value, and (d) bonding inner leads of lead frames to electrodes of semiconductor chips for the rest of lead frames in accordance with predetermined bonding site data without pictorially recognizing bonding sites thereof, if the statistic is equal to or smaller than the predetermined threshold value, or bonding inner leads of lead frames to electrodes of semiconductor chips for the rest of lead frames by pictorially recognizing bonding sites in adv

Abstract: A wire bonding device effects a bonding technique using ultrasonic waves to connect a chip having a semiconductor element and inner lead portions of a leadframe together by using metal fine wires. Herein, the wire bonding device employs a general-use leadframe, which is constructed in such a way that an angle of 0.degree. or 90.degree. is formed between the inner lead portions and frame. A frame guide is provided to transport the leadframes, which are placed at prescribed positions at a wire bonding mode. A bonding tool applies ultrasonic waves to connect the chip and the inner lead portions of the leadframe together by using the metal fine wires. An ultrasonic wave transmission arm holds the bonding tool at a tip portion thereof. The arm is capable of moving close to or apart from the leadframes, wherein a prescribed angle (e.g., 45.degree.) is kept between moving directions of the arm and longitudinal directions of all of the inner lead portions of the leadframes.

Abstract: A temperature balanced circuit is provided which is capable of, in case a CMOS.cndot.IC is utilized as a delay circuit, giving a constant delay time to an input signal to the delay circuit even if the frequency of the input signal is varied. A delay circuit 11 and a dummy circuit 11 having the same construction as that of the delay circuit are provided in a CMOS.cndot.IC. There are provided a counter counting first pulse signals CP1 supplied to the delay circuit during a fixed time interval and arithmetic unit finding a difference between a count value of this counter and a predetermined value, and the same number of second pulse signals as the difference value found by the arithmetic unit is supplied to the dummy circuit, thereby to define to a constant value both the number of the first pulses and the number of the second pulses supplied to the CMOS.cndot.IC within a unit time interval, which results in uniformity of an amount of heat generated in the CMOS.cndot.IC.

Abstract: A motor scooter with an enlarged storage compartment that decreases the overall bulk and weight of the vehicle. The storage compartment is effectively sealed to prevent water or spilled fuel from leaking therein, yet provides easy access to the engine located beneath it for purposes of maintenance and inspection. The contents of the storage compartment are protected from the heat generated by the engine which is in close proximity by an insulating wall construction.

Abstract: A shield for a motor scooter to protect the front legs of the operator. The shield includes extension panels pivotally mounted about hinges to the upper front panel. The extension panels may be oriented to assume multiple positions which can selectively remove the panels from the windstream, direct additional air toward the rider and provide additional shielding against air flow. Hinge mechanisms including oblong hinge pins are employed to provide various stable positions for the extension panels.