Patents by Inventor Takeo Murakami
Takeo Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9898434Abstract: A system includes: a first processor; a second processor; and a communication bus configured to couple the first processor and the second processor; wherein the first processor is configured to obtain a bus usage rate by monitoring a delay time period of data transfer in the communication bus, determine whether to offload a processing on received data based on the monitored bus usage rate, and offload the processing to the second processor when the processing is determined to be offloaded.Type: GrantFiled: January 21, 2016Date of Patent: February 20, 2018Assignee: FUJITSU LIMITEDInventor: Takeo Murakami
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Patent number: 9875517Abstract: A data processing method performed by a first processor configured to control a second processor that performs a process of creating an image and has a plurality of operation modes with different power consumption levels, the data processing method includes setting a number related to a second period following a first period based on a number of first images created by the second processor during the first period; and switching an operation mode of the second processor to an operation mode in which power consumption is lower than a power consumption of an operation mode during creating the image, among the plurality of operation modes, when the number of second images created during the second period reaches the set number.Type: GrantFiled: February 25, 2015Date of Patent: January 23, 2018Assignee: FUJITSU LIMITEDInventors: Masaaki Noro, Takeo Murakami
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Publication number: 20170310479Abstract: To enable multiple key replacements for information sharing between users and control of the key replacement directions, a key replacement direction control system 100 at least has a key replacement server 200 including: a storage part 220 that stores key replacement information defining a relation indicating permission and direction of information sharing between users, a replacement key for use to re-encrypt encrypted data of a first user to enable a second user to decrypt the encrypted data with a decryption key retained by the second user, and encrypted data of users; and an arithmetic device 210 that receives a transmission request from a user terminal, and if the key replacement information defines that information sharing in a direction from a certain user to a different user is permitted, re-encrypts encrypted data of the certain user using the replacement key for the users thus defined and transmits the re-encrypted encrypted data to the user terminal of the different user.Type: ApplicationFiled: October 26, 2015Publication date: October 26, 2017Inventors: Hisayoshi SATO, Kiminori NAKAMURA, Takeo MURAKAMI
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Patent number: 9563931Abstract: A control method executed by an information processing device including a first processor and a second processor includes specifying a plurality of processes which issued orders for causing the first processor to execute a drawing process for drawing a frame, the plurality of processes being executed by the second processor, first determining whether the drawing process is completed, based on a comparison between the specified plurality of processes and specific processes, and controlling, based on a result of the first determining, a state regarding a power consumption of the first processor until the first processor starts another drawing process for drawing another frame.Type: GrantFiled: March 4, 2015Date of Patent: February 7, 2017Assignee: FUJITSU LIMITEDInventors: Takeo Murakami, Masaaki Noro
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Patent number: 9529407Abstract: A method of controlling an apparatus including a processor including a plurality of cores, the method includes, when a number of the cores to be activated is M, determining whether or not a first power consumed by the M activated core is within a range of a second power to be consumed when the number of the cores to be activated is M+N, and when the first power is out of the range of the second power, prohibiting to increase the number of the cores to be activated from M to M+N.Type: GrantFiled: January 17, 2014Date of Patent: December 27, 2016Assignee: FUJITSU LIMITEDInventor: Takeo Murakami
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Patent number: 9513685Abstract: A method of measuring a processing load of a processor in executing a thread. When the load is above a threshold, measuring repeatedly at a first time interval, and when lower than the threshold, measuring repeatedly at a second, longer time interval.Type: GrantFiled: June 13, 2014Date of Patent: December 6, 2016Assignee: FUJITSU LIMITEDInventor: Takeo Murakami
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Publication number: 20160217091Abstract: A system includes: a first processor; a second processor; and a communication bus configured to couple the first processor and the second processor; wherein the first processor is configured to obtain a bus usage rate by monitoring a delay time period of data transfer in the communication bus, determine whether to offload a processing on received data based on the monitored bus usage rate, and offload the processing to the second processor when the processing is determined to be offloaded.Type: ApplicationFiled: January 21, 2016Publication date: July 28, 2016Applicant: FUJITSU LIMITEDInventor: Takeo Murakami
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Patent number: 9372714Abstract: An information terminal apparatus includes a memory and a processor. The memory stores information indicating a front operating system. The processor runs a first virtual machine that executes a first operating system. The processor runs a second virtual machine that executes a second operating system. The processor controls user interface of the information terminal apparatus by executing the front operating system. The processor detects, by referring to the information stored in the memory, that the front operating system is changed from the first operating system to the second operating system. The processor notifies, upon the detection, the first virtual machine of a first notification indicating that the user interface stops. The processor notifies, upon the detection, the second virtual machine of a second notification indicating that the user interface restarts.Type: GrantFiled: April 25, 2012Date of Patent: June 21, 2016Assignee: FUJITSU LIMITEDInventors: Yasushi Hara, Katsumi Otsuka, Masahide Noda, Takeo Murakami
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Publication number: 20150301586Abstract: A control method executed by an information processing device including a first processor and a second processor includes specifying a plurality of processes which issued orders for causing the first processor to execute a drawing process for drawing a frame, the plurality of processes being executed by the second processor, first determining whether the drawing process is completed, based on a comparison between the specified plurality of processes and specific processes, and controlling, based on a result of the first determining, a state regarding a power consumption of the first processor until the first processor starts another drawing process for drawing another frame.Type: ApplicationFiled: March 4, 2015Publication date: October 22, 2015Applicant: Fujitsu LimitedInventors: Takeo MURAKAMI, Masaaki Noro
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Publication number: 20150301585Abstract: A data processing method performed by a first processor configured to control a second processor that performs a process of creating an image and has a plurality of operation modes with different power consumption levels, the data processing method includes setting a number related to a second period following a first period based on a number of first images created by the second processor during the first period; and switching an operation mode of the second processor to an operation mode in which power consumption is lower than a power consumption of an operation mode during creating the image, among the plurality of operation modes, when the number of second images created during the second period reaches the set number.Type: ApplicationFiled: February 25, 2015Publication date: October 22, 2015Applicant: FUJITSU LIMITEDInventors: Masaaki NORO, Takeo Murakami
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Publication number: 20150241951Abstract: A data processing method for updating a picture to be displayed in a display, based on a synchronization signal issued in each predetermined time period, the data processing method including calculating a scheduled number of sub-pictures scheduled to be created by a processor in a first time period from issuing of a first synchronization signal until the predetermined time period elapses, the sub-pictures being pieces of pictures included in the picture to be displayed in the display, counting an actual number of sub-pictures created by the processor in the first time period, detecting that the actual number of sub-pictures reaches the scheduled number of sub-pictures; and reducing power consumption of the processor, based on the detecting that the actual number of sub-pictures reaches the scheduled number of sub-pictures.Type: ApplicationFiled: January 7, 2015Publication date: August 27, 2015Applicant: FUJITSU LIMITEDInventors: Masaaki NORO, Takeo Murakami
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Patent number: 9058173Abstract: A method for controlling a mobile terminal device that includes a multi-core CPU and a display that displays an execution result of an application program executed by the multi-core CPU includes detecting an application program of which an execution result is displayed, calculating a CPU load per thread in the application program detected in the detecting, and increasing the number of cores operating in the multi-core CPU when the number of threads, each of the threads causing the CPU load to be equal to or higher than a first value, is equal to or higher than a second value.Type: GrantFiled: August 23, 2012Date of Patent: June 16, 2015Assignee: FUJITSU LIMITEDInventor: Takeo Murakami
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Patent number: 8954774Abstract: A computer system for managing a plurality of virtual machines, the computer system including: a processor; and a memory coupled to the processor, wherein the processor executes a process includes: recording, on the memory, an operation history of a virtual machine that is related to a user operation in the plurality of virtual machines; determining whether the user operation is performed or not at switching of the virtual machines by referring to the operation history and comparing an operation time of the virtual machine that has operated most recently with the operation time of a control table, the control table being stored in the memory; and increasing an operation frequency of a CPU when performance of the user operation is detected.Type: GrantFiled: May 24, 2012Date of Patent: February 10, 2015Assignee: Fujitsu LimitedInventors: Takeo Murakami, Masahide Noda, Masatomo Yasaki
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Publication number: 20150033240Abstract: A measuring method of a processing load of a processor, the method includes measuring a first processing load of the processor in executing of a first thread included in a program at a first frequency, the first processing load is equal to or higher than a first threshold, and measuring a second processing load of the processor in executing of a second thread included in the program at a second frequency lower than the first frequency, the second processing load is lower than the first threshold.Type: ApplicationFiled: June 13, 2014Publication date: January 29, 2015Applicant: FUJITSU LIMITEDInventor: Takeo MURAKAMI
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Publication number: 20140237274Abstract: A method of controlling an apparatus including a processor including a plurality of cores, the method includes, when a number of the cores to be activated is M, determining whether or not a first power consumed by the M activated core is within a range of a second power to be consumed when the number of the cores to be activated is M+N, and when the first power is out of the range of the second power, prohibiting to increase the number of the cores to be activated from M to M+N.Type: ApplicationFiled: January 17, 2014Publication date: August 21, 2014Applicant: FUJITSU LIMITEDInventor: Takeo MURAKAMI
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Patent number: 8707109Abstract: A computer apparatus includes a managing unit realizing virtual computers including device driver virtual computers and user virtual computers, the user virtual computers communicating with various devices via the device driver virtual computers. Error detection information is received from one of the virtual computers upon detection of error in one of the device drivers used for communication with one of the devices in one of the virtual computers. One or more types of the virtual computers and the contents of recovery process corresponding to the type of device driver and the type of error indicated in the received error detection information are acquired from error recovery control information. A recovery instruction is transmitted to one or more of the virtual computers identified by the one or more acquired types of virtual computers in order to cause the one or more identified virtual computers to perform the acquired contents of the recovery process.Type: GrantFiled: April 26, 2011Date of Patent: April 22, 2014Assignee: Fujitsu LimitedInventors: Takeo Murakami, Masahide Noda
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Publication number: 20130346991Abstract: A method of controlling an information processing apparatus includes detecting a first application program of which an execution result is displayed, obtaining a parameter correlating to the first application program, and determining, by a processor, the number of cores to be run in a CPU on a basis of the parameter.Type: ApplicationFiled: April 23, 2013Publication date: December 26, 2013Applicant: FUJITSU LIMITEDInventor: Takeo MURAKAMI
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Publication number: 20130103956Abstract: A method for controlling a mobile terminal device that includes a multi-core CPU and a display that displays an execution result of an application program executed by the multi-core CPU includes detecting an application program of which an execution result is displayed, calculating a CPU load per thread in the application program detected in the detecting, and increasing the number of cores operating in the multi-core CPU when the number of threads, each of the threads causing the CPU load to be equal to or higher than a first value, is equal to or higher than a second value.Type: ApplicationFiled: August 23, 2012Publication date: April 25, 2013Applicant: FUJITSU LIMITEDInventor: Takeo MURAKAMI
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Publication number: 20130007493Abstract: A computer system for managing a plurality of virtual machines, the computer system including: a processor; and a memory coupled to the processor, wherein the processor executes a process includes: recording, on the memory, an operation history of a virtual machine that is related to a user operation in the plurality of virtual machines; determining whether the user operation is performed or not at switching of the virtual machines by referring to the operation history and comparing an operation time of the virtual machine that has operated most recently with the operation time of a control table, the control table being stored in the memory; and increasing an operation frequency of a CPU when performance of the user operation is detected.Type: ApplicationFiled: May 24, 2012Publication date: January 3, 2013Applicant: FUJITSU LIMITEDInventors: Takeo MURAKAMI, Masahide NODA, Masatomo YASAKI
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Publication number: 20120311578Abstract: An information terminal apparatus includes a memory and a processor. The memory stores information indicating a front operating system. The processor runs a first virtual machine that executes a first operating system. The processor runs a second virtual machine that executes a second operating system. The processor controls user interface of the information terminal apparatus by executing the front operating system. The processor detects, by referring to the information stored in the memory, that the front operating system is changed from the first operating system to the second operating system. The processor notifies, upon the detection, the first virtual machine of a first notification indicating that the user interface stops. The processor notifies, upon the detection, the second virtual machine of a second notification indicating that the user interface restarts.Type: ApplicationFiled: April 25, 2012Publication date: December 6, 2012Applicant: FUJITSU LIMITEDInventors: Yasushi HARA, Katsumi OTSUKA, Masahide NODA, Takeo MURAKAMI