Patents by Inventor Takeo Nakayama

Takeo Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240090344
    Abstract: A magnetic storage device includes first and second magnetic layers and a non-magnetic layer, where the non-magnetic layer includes a first oxide layer containing magnesium and oxygen, a second oxide layer containing magnesium and oxygen, a third oxide layer containing zinc and oxygen, a fourth oxide layer containing a first predetermined element and oxygen, and a fifth oxide layer containing a second predetermined element and oxygen, and a crystal structure of an oxide of the first predetermined element and a crystal structure of an oxide of the second predetermined element are each a rock salt structure. The first predetermined element and the second predetermined element each have an oxide formation free energy greater than an oxide formation free energy of zinc, and the oxide of the first predetermined element and the oxide of the second predetermined element each have a bandgap narrower than a bandgap of an oxide of magnesium.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 14, 2024
    Inventors: Takeo KOIKE, Rina NOMOTO, Hiroyuki KANAYA, Masahiko NAKAYAMA, Daisuke WATANABE
  • Patent number: 9809087
    Abstract: A foreign object obstruction device for preventing foreign objects from entering into the vent of a vehicle without completely obstructing the air passage of the vent is provided. The foreign object obstruction device extends between the a rear vehicle bumper and the vehicle body, and includes a rigid panel mounted to the vehicle body, generally beneath the vent so as to present a generally horizontal planar surface. The foreign object obstruction device may also include a stand-off structure extending from the rigid panel to the vehicle body so as to maintain the foreign obstruction device a predetermined distance from the vent, and a resilient pad disposed between the stand-off structure and the vehicle body so as to help absorb the force caused by objects being hurled into the device; and between the rigid panel and the bumper so as to form a seal.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: November 7, 2017
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: David Takeo Nakayama
  • Patent number: 8465089
    Abstract: A rocker molding for attachment to a rocker panel of a vehicle includes a rocker garnish with an arcuate cross section. A garnish shelf extends from an upper edge of the rocker garnish such that the garnish shelf is substantially perpendicular to the rocker garnish. A riser portion extends from an inboard edge of the garnish shelf in a substantially vertical direction. A cap shelf extends from a top edge of the riser portion in an inboard direction. When the rocker molding is installed on the rocker panel of the vehicle, the garnish shelf extends from the rocker panel in an outboard direction, the riser portion is substantially flush with a skin of a vehicle door when the door is in a closed position, and a bottom edge of the vehicle door is spaced apart from the garnish shelf by at least a height H of the riser portion.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: June 18, 2013
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Aaron W. J. Atkinson, Peter Kim, David Takeo Nakayama
  • Publication number: 20130069396
    Abstract: A rocker molding for attachment to a rocker panel of a vehicle includes a rocker garnish with an arcuate cross section. A garnish shelf extends from an upper edge of the rocker garnish such that the garnish shelf is substantially perpendicular to the rocker garnish. A riser portion extends from an inboard edge of the garnish shelf in a substantially vertical direction. A cap shelf extends from a top edge of the riser portion in an inboard direction. When the rocker molding is installed on the rocker panel of the vehicle, the garnish shelf extends from the rocker panel in an outboard direction, the riser portion is substantially flush with a skin of a vehicle door when the door is in a closed position, and a bottom edge of the vehicle door is spaced apart from the garnish shelf by at least a height H of the riser portion.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Aaron W.J. Atkinson, Peter Kim, David Takeo Nakayama
  • Publication number: 20120126096
    Abstract: According to one embodiment, a semiconductor layer in which a photoelectric conversion unit is formed for each pixel, a readout circuit that is formed on a front side of the semiconductor layer and reads out a signal from the photoelectric conversion unit, a light incident surface provided on a back side of the photoelectric conversion unit, and a gettering layer provided on a front side of the photoelectric conversion unit are included.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki SUGIURA, Takeo Nakayama
  • Patent number: 8172313
    Abstract: A side outer panel of a vehicle having an outer surface including an outer surface edge. The outer surface edge has a predetermined curved path that provides a styling shape to add an aesthetic element to the side outer panel. The side outer panel further includes a mounting portion integrally formed thereto. The mounting portion provides a structure for attaching the side outer panel to the vehicle. In a preferred embodiment, the mounting portion includes a planar surface spaced apart from the outer surface and a step disposed between the outer surface edge and the planar surface. The planar surface at least one flange extending orthogonally therefrom to define a welding surface for welding the side outer panel to the body thereby providing structural reinforcement to the outer surface edge of the side outer panel.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: May 8, 2012
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Jeffrey Brian Wolbert, David Takeo Nakayama, Nigel Christopher Taylor
  • Publication number: 20100130116
    Abstract: A foreign object obstruction device for preventing foreign objects from entering into the vent of a vehicle without completely obstructing the air passage of the vent is provided. The foreign object obstruction device extends between the a rear vehicle bumper and the vehicle body, and includes a rigid panel mounted to the vehicle body, generally beneath the vent so as to present a generally horizontal planar surface. The foreign object obstruction device may also include a stand-off structure extending from the rigid panel to the vehicle body so as to maintain the foreign obstruction device a predetermined distance from the vent, and a resilient pad disposed between the stand-off structure and the vehicle body so as to help absorb the force caused by objects being hurled into the device; and between the rigid panel and the bumper so as to form a seal.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: David Takeo Nakayama
  • Publication number: 20100032986
    Abstract: A side outer panel of a vehicle having an outer surface including an outer surface edge. The outer surface edge has a predetermined curved path that provides a styling shape to add an aesthetic element to the side outer panel. The side outer panel further includes a mounting portion integrally formed thereto. The mounting portion provides a structure for attaching the side outer panel to the vehicle. In a preferred embodiment, the mounting portion includes a planar surface spaced apart from the outer surface and a step disposed between the outer surface edge and the planar surface. The planar surface at least one flange extending orthogonally therefrom to define a welding surface for welding the side outer panel to the body thereby providing structural reinforcement to the outer surface edge of the side outer panel.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 11, 2010
    Applicant: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Jeffrey Brian Wolbert, David Takeo Nakayama, Nigel Christopher Taylor
  • Publication number: 20030102530
    Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same.
    Type: Application
    Filed: January 6, 2003
    Publication date: June 5, 2003
    Applicant: Kabushiki Kaisha Toshiba.
    Inventors: Masahiko Matsumoto, Hisato Oyamatsu, Takeo Nakayama, Yasuhiro Fukaura, Kunihiro Kasai, Masahiro Inohara
  • Patent number: 6525402
    Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: February 25, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Matsumoto, Hisato Oyamatsu, Takeo Nakayama, Yasuhiro Fukaura, Kunihiro Kasai, Masahiro Inohara
  • Patent number: 6436776
    Abstract: A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 20, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Nakayama, Akira Hokazono
  • Patent number: 6396146
    Abstract: Dummy patterns are formed in signal patterns of a first metal layer, an insulating film covering such patterns is flattened by CMP, and only dummy patterns are selectively etched by anisotropic etching through holes opened at specific intervals. Then the opened holes are filled with an insulating film, and cavities are formed. In the upper part of the cavity, a signal line of the second metal layer is formed. As a result, a semiconductor device is provided by the CMP flattening technology without being accompanied by increase of parasitic capacity between signal lines by metal dummy patterns or shorting due to dust and the like.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: May 28, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Nakayama
  • Publication number: 20020000663
    Abstract: Dummy patterns are formed in signal patterns of a first metal layer, an insulating film covering such patterns is flattened by CMP, and only dummy patterns are selectively etched by anisotropic etching through holes opened at specific intervals. Then the opened holes are filled with an insulating film, and cavities are formed. In the upper part of the cavity, a signal line of the second metal layer is formed. As a result, a semiconductor device is provided by the CMP flattening technology without being accompanied by increase of parasitic capacity between signal lines by metal dummy patterns or shorting due to dust and the like.
    Type: Application
    Filed: November 19, 1998
    Publication date: January 3, 2002
    Inventor: TAKEO NAKAYAMA
  • Publication number: 20010034085
    Abstract: A shallow impurity diffusion layer adjacent to a gate electrode is formed by forming a side-wall insulating film of the gate electrode twice, and a MOS transistor of the salicide type having improved short-channel effect is embodied. An impurity diffusion layer portion not adjacent to a gate electrode of a source/drain region is formed first by self-alignment with a first side-wall insulating film. After an impurity diffusion layer adjacent to the gate electrode is formed by self-alignment with the gate electrode, a second side-wall insulating film is formed. Silicide films are formed on the gate electrode and source/drain region by self-alignment with the second side-wall insulating film.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 25, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeo Nakayama, Akira Hokazono
  • Patent number: 5442226
    Abstract: In a semiconductor device, an emitter electrode has a polysilicon layer provided in a first contact hole and on a first insulating film. The polysilicon layer is in contact with an emitter region and is covered with a metal layer. A second contact hole is provided on a part of a second insulating film located on a substantially flat portion of the metal layer. A third contact hole is provided in those portions of the first insulating film and a second insulating layer which are located on a base region.
    Type: Grant
    Filed: April 26, 1993
    Date of Patent: August 15, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Hiroshi Gojohbori, Takeo Nakayama
  • Patent number: 5396105
    Abstract: A MOSFET constituting a flip-flop circuit and a MOSFET for control of reading and writing data out of and into a memory cell are formed on a semiconductor. The gate electrode of the first MOSFET and the gate electrode of the second MOSFET are formed by layers of different levels. The gate electrodes have an overlapped portion R. The first and second MOSFETs are arranged symmetrically with respect to a certain point P. By virtue of the above structure, the degree of integration of a static RAM is enhanced.
    Type: Grant
    Filed: September 4, 1992
    Date of Patent: March 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Nakayama
  • Patent number: 4994894
    Abstract: A semiconductor device comprises a semiconductor substrate having a diffused region and an element region, and the diffused region and the element region overlap at least partially. An insulating layer having a contact hole is provided at the surface of the substrate. A wiring layer crosses over the contact hole to form at least four crossing points with respect to the contact hole. The crossing points over the element region correspond to the overlap between the diffused region and the element region.
    Type: Grant
    Filed: January 5, 1989
    Date of Patent: February 19, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Nakayama
  • Patent number: 4806585
    Abstract: A one-can resin composition which contains:(1) a blocked polyisocyanate produced by blocking, with an oxime type blocking agent, .alpha.,.alpha.,.alpha.',.alpha.'-tetra-methylxylylene diisocyanate or a terminal NCO-containing prepolymer formed by reaction of said diisocyanate with an active hydrogen-containing compound,(2) a polyol compound and(3) a monoalcohol.The resin composition, when stored at 40.degree. C., is stable for at least 3 months. It can be cured at temperatures as low as 90.degree.-120.degree. C. Therefore, it can be used advantageously as a baking paint for automotive exterior coating, cationic electro-deposition coating, coating of household electric appliances, and enameled wire manufacture, among others.
    Type: Grant
    Filed: September 15, 1987
    Date of Patent: February 21, 1989
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Takeo Nakayama, Takurou Sakamoto
  • Patent number: 4797449
    Abstract: A resin composition, which comprises (a) a copolymer containing isocyanate group prepared by subjecting a compound represented by the general formula ##STR1## wherein R.sub.1 stands for hydrogen or methyl group and an ethylenic unsaturated monomer to copolymerization, and (b) a copolymer containing amino group prepared by subjecting a compound represented by the general formula ##STR2## wherein R.sub.2 stands for hydrogen or methyl group and an ethylenic unsaturated monomer to copolymerization, has a pot life of such an extent as for permitting them to be used as spray-coating, and the resulting film is excellent in flexibility, chemical resistance, water resistance and corrosion resistance, and, besides, rapid in curability, thus being useful as cold-drying coatings on metals, plastics, woods, inorganic materials, etc. and also as adhesives, etc. The resin composition is very good in compatibility, thus being useful in such a field as required high gloss and beautiful finish.
    Type: Grant
    Filed: March 3, 1988
    Date of Patent: January 10, 1989
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Takeo Nakayama, Saburo Inoue, Takurou Sakamoto
  • Patent number: 4613652
    Abstract: A curable resin composition which comprises (1) a copolymer composed of an aminoalkyl acrylate and/or aminoalkyl methacrylate and an ethylenically unsaturated monomer being formulated with (2) a compound having at least two acryloyl groups in the molecule.The composition can be cured at low temperatures in the range of ordinary temperature to 120.degree. C., and therefore advantageously used for the formation of coating films in the application fields, such as plastics, wood and concrete, where heat treatment cannot be performed. Also, the composition which exhibits excellent adherence toward various kinds of substrates can be used as adhesives and different kinds of primers, as well. Furthermore, the composition can provide coating films that excel in terms of water resistance, weathering resistance and solvent resistance, and therefore be utilized for overpaints, etc.
    Type: Grant
    Filed: June 7, 1985
    Date of Patent: September 23, 1986
    Assignee: Takeda Chemical Industries, Inc.
    Inventors: Takeo Nakayama, Kimiya Fujinami, Takurou Sakamoto, Fumihiro Doura