Abstract: A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Abstract: A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Abstract: A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Abstract: A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.

Abstract: According to one embodiment, a logic verifying apparatus includes an input module, an extracting module, a table generator, and a verification information generator. The input module is configured to accept a first assertion and a first test pattern. The extracting module is configured to extract a definite rule assertion and a hold rule assertion by analyzing the first assertion accepted by the input module. The table generator is configured to generate a rule table indicating a relationship between the definite condition and a signal of the verification object circuit based on the definite rule assertion and hold rule assertion extracted by the extracting module. The verification information generator is configured to generate verification information used to verify a non-formulation behavior of the verification object circuit based on the rule table generated by the table generator.

Abstract: A circuit description generating apparatus has an ID addition part configured to add a common ID to a command inputted to a verification target circuit described by a circuit description language and data corresponding to the command, a bit width adjusting part configured to adjust a bit width of an ID of the command and an ID of the data along a signal path which pass through inside of the verification target circuit, and a circuit description generating part configured to generate a circuit description corresponding to the verification target circuit, the circuit description including the command and data with the IDs of which bit widths are adjusted by the bit width adjusting part.

Abstract: A circuit verification apparatus includes a code coverage measurement point extracting unit which reads a device-under-test circuit description written in a hardware description language and metrics information including information about multiple measurement objects, extracts multiple measurement points for code coverage measurement from the device-under-test circuit description, and generates a database including only predetermined measurement points among the extracted multiple measurement points. The circuit verification apparatus also includes an assertion converting unit configured to convert each of the predetermined measurement points to a corresponding assertion description and a code coverage result decompressing unit configured to receive the database and an assertion result obtained by performing measurement based on the assertion description and generate a code coverage result.

Abstract: There is provided with a circuit design verification method including: accepting input of a circuit description which describes a circuit by using a plurality of conditional statements each including one or more conditional elements; extracting each conditional statement included in the circuit description and each conditional element included in the conditional statements; executing the circuit description by using test data for the circuit; and generating a table including verification information for each conditional statement, the verification information representing (A1) whether each conditional element has been always true, (A2) whether each conditional element has been always false, or (A3) whether each conditional element has been both true and false when the conditional statement is satisfied.

Abstract: A computer implemented method for design verification using logical simulation of a circuit description having a plurality of hierarchies from top to bottom in accordance with abstraction of circuit components, which have an arithmetic and logic function, reads the circuit description and analyzes signal connection topologies between the hierarchies of the circuit description from top to bottom. The method stores the data of the signal connection topologies. The method reads properties of target modules implemented by the circuit components in the circuit description. The method extracts a property part having a signal communicating between the target modules. The method extracts an output operation property, defining output operation of an output side module, and an expecting operation property, defining an expecting operation of an input side module among the properties of the target modules. The method compares the output operation properties with the expecting operation properties.