Abstract: A sense amplifier circuit has a sense amplifier disposed on a bit line of an AND array circuit; a switch for selecting an output of the sense amplifier; a power switch for the sense amplifier; and a device for turning the power switch on by using a turning-on signal with respect to the switch for selecting the output of the sense amplifier. When the output of the sense amplifier is selected by the switch, the power switch is turned on by using the turning-on signal of this switch so that the sense amplifier is operated. When a turning-off signal is transmitted from the switch of the sense amplifier and the output of the sense amplifier is not selected, the power switch is turned off by this turning-off signal.

Abstract: A programmable logic array (PLA) whose AC characteristics such as an input-to-output delay characteristic can be measured includes a plurality of input lines, a plurality of product term lines, a plurality of non-volatile memory elements, and a test input line to which a test signal may be applied. Those non-volatile memory elements which are connected to the input lines other than the test input line are turned OFF in a test mode, while turning all product term lines other than the product term line whose AC characteristics are to be measured, to a low level. Only those memory elements whose AC characteristics are to be measured are operable in an ON-OFF fashion and only the product term line to be measured is ready to have a low level or a high level. When a test signal is applied to the test input line, it is routed to the operable memory elements and product term line only.

Abstract: A logic integrated circuit device includes a pair of input terminals, an OR gate having a pair of inputs coupled to the pair of input terminals, an exclusive OR gate having a pair of inputs coupled to the pair of input terminals, a first output terminal connected from one of the pair of input terminals through a first gate switch and also from the output of the OR gate through a second gate switch, and a second output terminal connected from the other of the pair of input terminals through a third gate switch and also from the output of the exclusive OR gate through a fourth gate switch. Also provided is a data read out circuit which is operatively coupled to the four gate switches through a switch control circuit.

Abstract: A programmable logic device include an AND gate array and an OR gate array, at least one of which is programmable by the user. The AND gate array includes a plurality of input lines, a plurality of product term lines which cross said plurality of input lines, and a plurality of programmable elements located at the intersections between the input and product term lines. An activation control circuit is also provided for activating at least one of the product term lines while keeping those product term lines which are not used for programming deactivated. With this structure, the waste of power can be minimized.