Abstract: A substrate treating apparatus disclosed herein realizes improved throughput. The substrate treating apparatus according to this invention includes an antireflection film forming block, a resist film forming block and a developing block arranged in juxtaposition. Each block includes chemical treating modules, heat-treating modules and a single main transport mechanism. The main transport mechanism transports substrates within each block. Transfer of the substrates between adjacent blocks is carried out through substrate rests. The main transport mechanism of each block is not affected by movement of the main transport mechanisms of the adjoining blocks. Consequently, the substrates may be transported efficiently to improve the throughput of the substrate treating apparatus.

Abstract: For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.

Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.

Abstract: The output circuit has an output transistor adjusted in driving capability, using a negative voltage or changing a transistor size in accordance with the level of output power supply voltage. Particularly, by increasing the driving capability of a P-channel MOS transistor for pulling up the output node, an output signal can be generated at high speed while suppressing reduction of the driving capability of the P-channel MOS transistor even under a low output power supply voltage condition. An output circuit that can drive an output node with an optimum driving capability even if an output power supply voltage is changed, is provided.

Abstract: A refresh array activating signal is Activated in accordance with a refresh request and specific address bit(s) of a refresh address. Specific lower bit(s) of a refresh address counter is (are) utilized as the specific address bit(s) of the refresh address, and the specific address bit(s) is (are) utilized as upper bit(s) of the refresh address. Thus, in the self-refresh mode, refresh can be performed for a prescribed address region at uniform intervals, with a lengthened refresh interval, consuming less current. A semiconductor memory device is provided which allows current consumption to be distributed on a time basis and to be reduce in a self-refresh mode is provided.

Abstract: A level conversion circuit is provided, at an output, with an initialization circuit for setting the output signal of the level conversion circuit for generating a power cut enable signal controlling a deep power down mode to a predetermined inactive state upon power up. The initialization circuit is constituted by, for example, a capacitive element connected to the output node of the level conversion circuit to pull up the voltage of the output node upon power up, and a latch circuit latching the voltage level of the output node. When power is on, the power cut enable signal is forcibly inactivated by the initialization circuit to generate a periphery power supply voltage. The internal node of the level conversion circuit is initialized according to the output signal of a control circuit receiving the periphery power supply voltage as an operating power supply voltage.

Abstract: An input circuit is comprised of a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly.

Abstract: A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.

Abstract: For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.

Abstract: In the output circuit, at a subsequent stage of a gate circuit operating with a power supply voltage related to a first power supply voltage, a latch circuit formed of an inverter circuit and a MOS transistor is arranged, and is supplied with a second power supply voltage as an operating power supply voltage. An output buffer circuit is driven in accordance with an output signal of the latch circuit. When the first power supply voltage is powered down, the latch circuit receiving and operating with the second power supply voltage holds a signal voltage to be attained in a standby state and thus the output buffer circuit is reliably held in an output high impedance state. In a semiconductor device of a double power supply configuration, even when one power supply is powered down, the output buffer circuit can reliably be set to an output high impedance state.

Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.

Abstract: A bias voltage having a positive temperature dependency is supplied to a current source that determines the operating current of a refresh timer that issues a refresh request to allow the driving current of the current source to have a positive temperature characteristic. In this manner, the refresh cycle of the refresh timer shortens the issue intervals when the temperature rises, and lengthens the issue intervals of the refresh request when the temperature decreases. Thus, the consumed current for the refresh at room temperature is reduced. Consequently, the consumed current in a self-refresh mode under the room temperature condition can be reduced.

Abstract: A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit, for the CAS latency of no less than two, stores read data in response to the second clock signal attaining the active state, and for the CAS latency of one, stores read data in response to the first clock signal and an equalization signal each attaining the active state.

Abstract: In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.

Abstract: In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.

Abstract: A repeater circuit, operative in response to a clock signal transmitted from an internal clock generation circuit on a clock signal line, outputs one of first and second clock signals depending on whether a CAS latency of one or that of two is applied. The first clock signal pulses twice for activation within the period of an external clock. An input/output circuit for the CAS latency of no less than two stores read data in response the second clock signal attaining the active state and for the CAS latency of one stores read data in response to the first clock signal and an equalization signal each attaining the active state.

Abstract: In a control circuit and an address buffer circuit, buffer circuits of plural types are provided to each of pin terminals and an input buffer of one type is activated according a state control signal group. In a standby state, current paths of the control buffer circuit and the address buffer circuit are selectively cut off according to a CS cut mode instructing signal stored in a mode register and an internal chip select signal. Furthermore, when a low power consumption mode is specified, a current path of a CLK buffer for generating an internal clock signal is cut off according to an external clock enable signal and a low power mode instructing signal, and the current paths of the control buffer circuit and the address buffer circuit are also cut-off.

Abstract: Data specifying details of refresh to be executed in the self-refresh mode is stored in a register circuit in a mode register. A refresh period and refresh region are determined according to data stored in register circuit and a refresh control circuit generates a control signal and a refresh address that are required for refresh. Stored data can be stably held in the self-refresh mode in which data holding is performed with reduced current consumption.

Abstract: Data for switching a slew rate of a data output circuit included in a data input/output circuit between a slew rate in a normal mode and a slow slew rate is stored in a mode register. According to the data stored in mode register, a slew rate setting signal is generated. According to a slew rate switching circuit, the slew rate of the data input/output circuit is switched between a slew rate in the normal mode and a slow slew rate slower than the slew rate in the normal mode. A data output circuit is achieved which occupies a small area, is capable of setting a slew rate slower than the slew rate in a normal mode and outputting data without causing an erroneous operation with a low consumption current even when the slew rate is adjusted.

Abstract: A robot (12) takes a wafer (3f) out of an indexer (1) and then transports the same to a heat processing part (41). A wafer (3e), which has already introduced in the heat processing part (41) is took out thereof by the robot (5). The wafer (3f) is introduced in the heat processing part (41) after a waiting time (18a) so that an excess heat processing in the heat processing part (41) can be avoided. The wafer (3e) is transported to a processing part (43) and introduced therein by the robot (5). After the robot (5) repeats the similar processings in processing parts (13, 42, 44), it returns to the wafer transferring robot (12) to receive a next wafer. At that time, the robot (5) waits for a predetermined time thereby a cycle time is adjusted. After the waiting, the robot (5) takes out the wafer (3f), which has been introduced in the heat processing part (41), out thereof. Since the cycle time is set in common for different lots, the waiting times (18a, 18b) are set individually for each lot.