Abstract: In a semiconductor integrated device having floating voltage portion pairs, a signal line crossing over or under the floating voltage portion pairs, and a non-floating voltage portion, a noise source equivalent to the signal line is provided between the floating voltage pairs and the non-floating voltage portion.

Abstract: A wafer scale integration device comprises a plurality of real chips formed in the center portion of a wafer and a plurality of dummy chips formed in the circumference of the wafer. The dummy chips only include relay pads, some of the relay pads are used for relaying bonding wires of power supply lines. Consequently, the power supply lines do not short-circuit at edge portions of the wafer, since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad connected to the bonding wire.

Abstract: A wafer-scale semiconductor memory device includes a wafer, and a plurality of memory chips formed on the wafer. The memory chips contain a memory chip which includes a storage circuit, and a switching transistor which selectively connects the storage circuit to a power supply line in response to a control signal. The memory chip also includes a control logic circuit which writes data into the storage circuit and reads out data from the storage circuit and which generates a logic signal used for controlling the transistor. Further, the memory chip includes a fail-safe circuit having a circuit element having a status showing whether or not the control logic circuit is malfunctioning.

Abstract: A semiconductor memory device carrying out a self-refresh operation in response to a refresh request signal. The device includes a memory cell array formed on a chip; a plurality of pseudo memory cells distributed and arranged on the chip, each having the same constitution as the memory cells in the memory cell array; a first circuit for monitoring the capacitor voltage in the pseudo memory cells; and a second circuit for generating the refresh request signal and charging each capacitor in the pseudo memory cells. When the potential of at least one of the capacitors in the pseudo cells falls below a predetermined level, the refresh request signal is generated, thereby enabling the device to lengthen a refresh interval as desired and to decrease power dissipation, while facilitating work requiring any adjustment.

Abstract: A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the receiving element, for switching the input supplied to the internal circuit between output signals generating from the test pattern generating circuit and the external signals, the output signals generated from the test pattern generated circuit being input to the internal circuit through the input switching circuit in a test mode, the external signals being input to the internal circuit through the input switching circuit in a usual mode; the test pattern generating circuit, the input switching circuit, and the internal circuit being provided on the same chip.

Abstract: A semiconductor memory device of multi-bit type which produces plural output signals corresponding to read-out data from one address at a time including memory device for storing data. In a plurality of output buffer stages for producing the output signals, the operation of the output buffer stages is based upon at least a timing signal. A device for operating the output buffer stages have predetermined time differences. The output signals having predetermined time differences are delivered from the output buffer stages.

Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

Abstract: A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.

Abstract: A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.

Abstract: A semiconductor memory device (10), including a conventional redundancy memory array (12) therein, is disclosed. The redundancy memory array (12) is used for compensating data being stored in a defective memory cell (13') of main memory cells (11) located in the memory device (10). An addressing device (15) for specifying one of the memory cells, activates both the main memory cells (11) and the redundancy memory array (12), and at the same time, both a detecting device (16) for detecting whether or not an address information (AI) to be supplied to the addressing device (15) specifies the defective memory cell (13'), and a switching device (17) for selecting either one of the systems of the main memory cells (11) and the redundancy memory array (12), in accordance with a resultant determination of the detecting device (16), are activated. The switching device (17) is connected between a main data bus (DB.sub.m), cooperating with the main memory cells (11), and a redundancy data bus (DB.sub.

Abstract: A semiconductor memory device including a plurality of memory blocks (1-1, 1-2, 1-3, 1-4) each including a plurality of memory cells (C.sub.00, C.sub.01, . . . , C.sub.31,127). When test data is transmitted from one selected memory cell within each of the memory blocks to one of data bus pairs connected to the memory blocks (DB.sub.1, DB.sub.1. . . , DB.sub.4, DB.sub.4), all of the test data on the data bus pairs is checked simultaneously by a read test circuit (10). The semiconductor memory device includes first and second power supply terminals and each of the memory blocks having the memory cells arranged in rows and columns.

Abstract: An integrated semiconductor memory device is formed on a semiconductor substrate of one conductivity type on which there are provided peripheral circuits consisting of a pluality of memory cells each containing a storage capacitor and an IG FET. The IG FET in each memory cell acts as a transfer gate which is disposed on a surface region having the same conductivity type as that of the substrate and higher impurity concentrations than that of the substrate. The transfer gate has a gate threshold value which is higher than that of the IG FET in the peripheral circuits and which is insensitive to a noise pulse supplied thereto, whereby the destruction of data by noise pulse can be effectively prevented.