Patents by Inventor Takeo Uchiyama

Takeo Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Physiologically active compound
    Patent number: 5428175
    Abstract: A physiologically active compound HS-1 having the following chemical structure is disclosed. This compound is prepared by culturing Chromobacterium violaceum, adding tryptophan and diethyldithiocarbamate (diethyldithiocarbamic acid) to the culture broth for reacting with the cells for producing HS-1 in the cells, and collecting the compound from the culture broth. This novel compound possesses antitumor and antimicrobial activity, and is effective as an antitumor agent or an antimicrobial agent.
    Type: Grant
    Filed: February 18, 1994
    Date of Patent: June 27, 1995
    Assignee: Snow Brand Milk Products Co., Ltd.
    Inventors: Tsutomu Hoshino, Takeo Uchiyama, Kenichi Kimura, Hidetoshi Takahashi, Makoto Yoshihama
  • Semiconductor memory system for use in logic LSI's
    Patent number: 5117390
    Abstract: A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: May 26, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Akimoto, Katsumi Ogiue, Takeo Uchiyama
  • Semiconductor memory system for use in logic LSI's
    Patent number: 5023835
    Abstract: A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.
    Type: Grant
    Filed: May 10, 1989
    Date of Patent: June 11, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Akimoto, Katsumi Ogiue, Takeo Uchiyama
  • Semiconductor memory device having a timing generator circuit which provides a write pulse signal which has an optional timing relationship with the chip select signal
    Patent number: 4970687
    Abstract: A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.
    Type: Grant
    Filed: June 8, 1988
    Date of Patent: November 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Masami Usami, Kazuhiro Akimoto, Takeo Uchiyama, Masato Iwabuchi