Patents by Inventor Takeru Yonaga
Takeru Yonaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7437645Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.Type: GrantFiled: February 23, 2007Date of Patent: October 14, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
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Patent number: 7333372Abstract: A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.Type: GrantFiled: October 6, 2004Date of Patent: February 19, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Hitoshi Tanaka, Hiroyuki Fukuyama, Takeru Yonaga
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Publication number: 20070208966Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.Type: ApplicationFiled: February 23, 2007Publication date: September 6, 2007Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
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Patent number: 7249295Abstract: A semiconductor test circuit including an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives serial data including a command code and control data. The controller receives a control signal from the input terminal and outputs an internal control signal. The setting circuit receives serial data from the input terminal and outputs it to the command generator in response to the internal control signal. The command generator then generates an interface signal based on this serial data. The switching circuit receives the signal from one of its ports and outputs the received signal to another port in response to the internal control signal and the command code, and the comparator compares the interface signal received from the command generator with the signal received from the switching circuit.Type: GrantFiled: March 28, 2003Date of Patent: July 24, 2007Assignee: Oki Electric Industry Co., Ltd.Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
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Patent number: 7225379Abstract: A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a pattern generation circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a data comparator which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance in accordance with the test pattern and the data output from the circuit to be tested.Type: GrantFiled: February 25, 2005Date of Patent: May 29, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Takeru Yonaga
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Patent number: 7114113Abstract: A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.Type: GrantFiled: August 26, 2003Date of Patent: September 26, 2006Assignee: Oki Electric Industry Co., Ltd.Inventors: Takeru Yonaga, Hiroyuki Fukuyama, Hitoshi Tanaka
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Publication number: 20050240842Abstract: A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a pattern generation circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a data comparator which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance in accordance with the test pattern and the data output from the circuit to be tested.Type: ApplicationFiled: February 25, 2005Publication date: October 27, 2005Applicant: Oki Electric Industry Co., Ltd.Inventor: Takeru Yonaga
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Publication number: 20050105348Abstract: A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.Type: ApplicationFiled: October 6, 2004Publication date: May 19, 2005Applicant: Oki Electric Industry Co., Ltd.Inventors: Hitoshi Tanaka, Hiroyuki Fukuyama, Takeru Yonaga
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Publication number: 20040097093Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.Type: ApplicationFiled: March 28, 2003Publication date: May 20, 2004Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
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Publication number: 20040044491Abstract: A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.Type: ApplicationFiled: August 26, 2003Publication date: March 4, 2004Inventors: Takeru Yonaga, Hiroyuki Fukuyama, Hitoshi Tanaka
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Patent number: 5790470Abstract: A decoder circuit prevented from multi-selection is disclosed. The decoder circuit has a pulse generator receiving an external clock signal and outputting a reset signal in response to the external clock signal, address counters receiving the external clock signal and outputting address count signals and address buffers coupled to the address counters respectively. Each of the address buffers receives an external address signal and the address count signal and outputs an internal address signal. The decoder circuit further has address predecoders coupled to the pulse generator and said address buffers. Each of the address predecoders decodes the internal address signals to output a predecode signal in response to the reset signal. The decoder circuit further has an address decoder coupled to the address predecoders. The address decoder decodes the predecode signals to output decode signals.Type: GrantFiled: January 17, 1997Date of Patent: August 4, 1998Assignee: Oki Electric Industry Co., Ltd.Inventor: Takeru Yonaga
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Patent number: 5444662Abstract: A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines.Type: GrantFiled: June 8, 1994Date of Patent: August 22, 1995Assignee: Oki Electric Industry Co., Ltd.Inventors: Takayuki Tanaka, Yoshimasa Sekino, Yoshihiro Murashima, Yasuhiro Tokunaga, Joji Ueno, Takeru Yonaga
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Patent number: 5420823Abstract: A semiconductor memory has sense amplifiers which are supplied with a first potential from a first supply line and a second potential from a second supply line. A switching element on the first supply line is controlled by the potential of the second supply line, its conductivity increasing as the potential of the second supply line moves toward the second potential. A similar switching element, controlled by the potential of the first supply line, can be provided on the second supply line.Type: GrantFiled: September 2, 1993Date of Patent: May 30, 1995Assignee: Oki Electric Industry Co., Ltd.Inventors: Takeru Yonaga, Jouji Ueno, Junichi Suyama