Abstract: A semiconductor storage device detects a temperature T0 at which an output voltage Vtemp of the temperature detecting circuit equals to an output voltage Vref0 of the reference voltage generating circuit. In the lower temperature range lower than the temperature T0, the value of the reference voltage Vref is reduced by a preset voltage ?V from an external power supply voltage Vdd by a variable voltage generating circuit. The lowered voltage (Vdd??V) is applied to the word line WL of the memory cell via the word line driver as a variable power supply voltage Vcp.

Abstract: A unit memory cell comprises first and second field effect transistors of a first conduction type, third and fourth field effect transistors of a second conduction type, and first and second resistance elements. A gate electrode of the first transistor is connected to a second node, a gate electrode of the second transistor is connected to a first node, a series connected structure constructed by connecting a source/drain path of the third transistor and the first resistance element in series is connected between the first node and a first bit line, a series-connected structure constructed by connecting a source/drain path of the fourth transistor and the second resistance element in series is connected between the second node and a second bit line paired with the first bit line, and both gate electrodes of the third and fourth field effect transistors are connected to a word line.

Abstract: A semiconductor device of the present invention includes a memory cell array comprised of a plurality of unit memory cells disposed in a row and column array and the unit memory cell comprises first and second field effect transistors of a first conduction type, third ad fourth field effect transistors of a second conduction type, and first and second resistance elements.

Abstract: In an electrostatic protection circuit of the present invention, a trigger voltage for causing snapback operation in MOSFET is reduced and circuit elements with low breakdown voltages can be protected. A protection nMOSFET having a drain connected to an input/output terminal and a source and a substrate that are grounded is provided. A diode array, composed of at least one diode, is connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. Finally, a resistor is connected between the gate of the protection nMOSFET and ground.

Abstract: In an electrostatic protection circuit of the present invention, a trigger voltage for causing snapback operation in MOSFET is reduced and circuit elements with low breakdown voltages can be protected. A protection nMOSFET having a drain connected to an input/output terminal and a source and a substrate that are grounded is provided. A diode array, composed of at least one diode, is connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. Finally, a resistor is connected between the gate of the protection nMOSFET and ground.

Abstract: In a Viterbi decoder, a sequence of branch metrics is derived from a received convolutional codeword sequence. The branch metric sequence is divided and supplied to add/compare/select (ACS) circuits where the divided branch metric sequences added to previous path metrics. Path metric sequences of maximum likelihood paths are determined by the ACS circuits and indicators identifying the maximum likelihood paths are produced. A pipelining circuit is provided for reordering, or pipelining state metrics of the path metrics of the maximum likelihood paths and supplying the pipelined state metrics to the ACS circuits. The indicators from the ACS circuits are used to recover an original bit sequence.

Abstract: A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a p-channel MOSFET from increasing. An n-type dopant is selectively ion-implanted into surface areas of a first pair of n-type source/drain regions and a surface area of a first gate electrode in an NMOS region at a first acceleration energy, thereby forming a first plurality of amorphous regions in the NMOS region. The n-type dopant is ion-implanted into surface areas of the second pair of p-type source/drain regions and a surface area of the second gate electrode in a PMOS region at a second acceleration energy lower than the first acceleration energy, thereby forming second plurality of amorphous regions in the PMOS region.

Abstract: A surface-treating agent for a high-temperature refractory material, essentially consisting of 35.0 to 50.0 wt % of sodium silicate, 1.0 to 10.0 wt % of lithium compound, 1.0 to 10.0 wt % of alkali borate, 1 to 10.0 wt % of an organic silicone compound represented by the formula, R--Si(OH).sub.2 Na, wherein R stands for an alkyl group of 1 to 12 carbon atoms, and water and having a viscosity of not more than 100 cps at 20.degree. C., and a method for the surface treatment of a high-temperature refractory material, essentially consisting of rapidly spraying the treating agent mentioned above onto the surface of the refractory material when it is at a temperature in the range of 500.degree. to 1200.degree. C., thereby forming a layer of the treating agent in a molten state, and retaining the layer at a temperature of at least 1100.degree. C.

Abstract: A system for controlling an industrial robot, which is simplified in operation and capable of direct-teaching safely all the time. The system is provided with means (131 and 132) for monitoring a magnitude of an external force applied to the forward end of a hand during direct teaching, so that the motion of the robot can be forcibly restricted when the external force reaches a predetermined value of thereabove. Furthermore, when the system is operated to be set in a direct teach mode, a process (136) of correcting the offset of a force sensor is performed automatically.

Abstract: A MOS SRAM comprising memory cells capable of taking up less areas is disclosed. The flip-flop of a memory cell is connected to a pair of bit lines through a pair of transfer MOSFETs each corresponding to a bit line. At least one, preferably one on the flip-flop side, of the source and drain regions of each transfer MOSFET has a higher resistance. This enables to prevent damage of data which may happen during readout even in the case of use of finer word lines, and therefore contributes to the realization of the SRAM cell taking up relatively less area.

Abstract: A rotor blade is manufactured by making a soft alloy into a blade body with a curved section, joining a hard alloy to the leading edge of the blade body, coating the back side surfaces of the leading and trailing edge portions of the blade by alternately giving at least one coat each of a Ni-Cr-B-Si alloy and WC by spraying and fusing the coats onto the backing surfaces, and then coating the entire front side surface of the blade in the same way.