Abstract: A data processing system with an apparatus for reducing loop processing time including an address reset circuit that resets the program counter and prefetch counter to the loop beginning address when the program executes the instruction at the loop ending address. The need for repeated address calculation for branching to a loop beginning address after each loop execution cycle is eliminated, thereby speeding up the loop processing.

Abstract: A data bus buffer control circuit which is capable of delaying a data bus buffer output for a period corresponding to an arbitrary number of clock periods. A counter provided at an output of a write data output delay selection device is presettable by a read/write signal during read periods so that the number of clock periods to be preset is varied according to a desired delay. The counter counts the clock signal supplied through a logic circuit after commencement of the write cycle. When the content of the counter reaches the desired value, it provides an output by which the data bus buffer is enabled. Since the delay of the write data output is set every read cycle, it is possible to provide an optimum delay of the write data output for an accessed device and to interface low speed devices by increasing the number of bits of the counter.