Patents by Inventor Takeshi Chino
Takeshi Chino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10211119Abstract: An electronic component built-in substrate includes an insulating base material having a first surface and a second surface opposite to the first surface, an electronic component embedded in the insulating base material and having an electrode on a side surface thereof, a first wiring layer embedded in an area outside the electrode of the electronic component in the insulating base material with a surface of the first wiring layer being exposed from the first surface of the insulating base material, a via conductor reaching from the second surface of the insulating base material to a side surface of the electrode of the electronic component and the first wiring layer, and a second wiring layer formed on the second surface of the insulating base material and connected to the via conductor.Type: GrantFiled: May 24, 2016Date of Patent: February 19, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yasuhiko Kusama, Hironobu Hashimoto, Takeshi Chino, Kazuhiro Kobayashi
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Publication number: 20160353576Abstract: An electronic component built-in substrate includes an insulating base material having a first surface and a second surface opposite to the first surface, an electronic component embedded in the insulating base material and having an electrode on a side surface thereof, a first wiring layer embedded in an area outside the electrode of the electronic component in the insulating base material with a surface of the first wiring layer being exposed from the first surface of the insulating base material, a via conductor reaching from the second surface of the insulating base material to a side surface of the electrode of the electronic component and the first wiring layer, and a second wiring layer formed on the second surface of the insulating base material and connected to the via conductor.Type: ApplicationFiled: May 24, 2016Publication date: December 1, 2016Inventors: Yasuhiko Kusama, Hironobu Hashimoto, Takeshi Chino, Kazuhiro Kobayashi
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Patent number: 7196426Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: GrantFiled: November 24, 2004Date of Patent: March 27, 2007Assignee: Shinko Electric Industries Co., Ltd.Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Patent number: 7164198Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: GrantFiled: August 28, 2003Date of Patent: January 16, 2007Assignee: Shinko Electric Industres, Co., Ltd.Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Patent number: 7093356Abstract: A wiring substrate with bumps protruding from a surface of the substrate covers one side of a metallic base with an electrical insulating film thereon, having open holes exposing the base, etching the base through the open holes to form concavities in the base, electroplating the interior faces of the concavities to form a barrier metal film thereon filling the concavities with a bump material by electroplating, and forming a barrler layer on the bump material in each concavity. A stack of wiring patterns is formed on the insulating film, adjacent wiring patterns being separated by a respective intervening insulating layer and being electrically connected to each other through vias in the intervening insulating layer, and to the bump material filled in the concavities. Thereafter, the base and barrier metal film are removed.Type: GrantFiled: September 15, 2003Date of Patent: August 22, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Tadashi Kodaira, Takeshi Chino, Jyunichi Nakamura, Miwa Abe
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Patent number: 6988312Abstract: The invention relates a method for producing a multilayer circuit board (50) for a semiconductor device, comprising using a composite metal sheet (14) in which two metal sheets are combined, forming, on each side of the composite metal sheet, pads for connecting to a semiconductor element, the pads being made of a metal material which is substantially not etched by an etchant for the metal sheet, and an insulating layer having openings exposing the pads, forming, on the insulating layer, a wiring line layer (26) connected to the pads and having pads for connecting to another wiring line layer to be subsequently formed, subsequently fabricating a multilayer circuit board body (20) by necessary numbers of insulating layers and wiring line layers alternately formed, forming, on the outermost insulating layer of the multilayer circuit board body, an insulating layer provided with through-holes exposing pads for external connecting terminals, which are located on the outermost insulating layer, then dividing the cType: GrantFiled: October 29, 2002Date of Patent: January 24, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Jyunichi Nakamura, Shunichiro Matsumoto, Tadashi Kodaira, Hironari Aratani, Takanori Tabuchi, Takeshi Chino, Kiyotaka Shimada
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Publication number: 20050087860Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: ApplicationFiled: November 24, 2004Publication date: April 28, 2005Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Patent number: 6759739Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: GrantFiled: October 28, 2002Date of Patent: July 6, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Publication number: 20040074088Abstract: The invention relates a method for producing a multilayer circuit board (50) for a semiconductor device, comprising using a composite metal sheet (14) in which two metal sheets are combined, forming, on each side of the composite metal sheet, pads for connecting to a semiconductor element, the pads being made of a metal material which is substantially not etched by an etchant for the metal sheet, and an insulating layer having openings exposing the pads, forming, on the insulating layer, a wiring line layer (26) connected to the pads and having pads for connecting to another wiring line layer to be subsequently formed, subsequently fabricating a multilayer circuit board body (20) by necessary numbers of insulating layers and wiring line layers alternately formed, forming, on the outermost insulating layer of the multilayer circuit board body, an insulating layer provided with through-holes exposing pads for external connecting terminals, which are located on the outermost insulating layer, then dividing the cType: ApplicationFiled: November 14, 2003Publication date: April 22, 2004Inventors: Jyunichi Nakamura, Shunichiro Matsumoto, Tadashi Kodaira, Hironari Aratani, Takanori Tabuchi, Takeshi Chino, Kiyotaka Shimada
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Publication number: 20040060174Abstract: A method for producing a wiring substrate provided with bumps protruding from a surface of the substrate, the method comprising the steps of: covering one side of a metallic base with an electrical insulating film and forming open holes in the insulating film so as to expose at the bottoms thereof the base, etching the base using the insulating film having the open holes formed as a mask to form concavities in the base, electroplating the interior face of each of the concavities using the base as a plating power supply layer to form a barrier metal film on the interior face of each concavities, filling the concavities with a material for the bump by electroplating using the base as a plating power supply layer, forming a barrier layer on the surface of the material for the bump filled in each of the concavities using the base as a plating power supply layer, forming a stack of a predetermined number of wiring patterns on the insulating film, the adjacent wiring patterns in the stack being separated from eachType: ApplicationFiled: September 15, 2003Publication date: April 1, 2004Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.Inventors: Kei Imafuji, Tadashi Kodaira, Takeshi Chino, Jyunichi Nakamura, Miwa Abe
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Publication number: 20040046244Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: ApplicationFiled: August 28, 2003Publication date: March 11, 2004Applicant: Shinko Electric Industries Co., Ltd.Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Publication number: 20030080409Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: ApplicationFiled: October 28, 2002Publication date: May 1, 2003Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino