Patents by Inventor Takeshi Fujimori

Takeshi Fujimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107200
    Abstract: A solid-state imaging device includes a pixel array that is quadrilateral and includes pixels arranged in rows and columns, where each of the pixels accumulates an electric charge resulting from photoelectric conversion. The pixel array includes: a first area including first pixels for obtaining a captured image; and a second area including a second pixel for individually identifying the solid-state imaging device. The second area is provided in the vicinity of at least one corner among four corners of the pixel array, where the vicinity is a range of a predetermined number of pixels away from the at least one corner. The second pixel includes circuit elements or optical elements different from circuit elements or optical elements in each of the first pixels.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Yoshihisa FUJIMORI, Yasuhiro KOSAKA, Takeshi SOWA, Kazuaki SOGAWA
  • Patent number: 11939219
    Abstract: The carbon nanotube assembled wire includes a plurality of carbon nanotubes oriented at a degree of orientation of 0.9 or more and 1 or less.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 26, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., UNIVERSITY OF TSUKUBA
    Inventors: Toshihiko Fujimori, Takeshi Hikata, Soichiro Okubo, Jun-ichi Fujita
  • Patent number: 11919164
    Abstract: A robot system (1) includes the robot (10), a motion sensor (11), a surrounding environment sensor (12, 13), an operation apparatus (21), a learning control section (41), and a relay apparatus (30). The robot (10) performs work based on an operation command. The operation apparatus (21) detects and outputs an operator-operating force applied by the operator. The learning control section (41) outputs a calculation operating force. The relay apparatus (30) outputs the operation command based on the operator-operating force and the calculation operating force. The learning control section (41) estimates and outputs the calculation operating force by using a model constructed by performing the machine learning of the operator-operating force, the surrounding environment data, the operation data, and the operation command based on the operation data and the surrounding environment data outputted by the sensors (11 to 13), and the operation command outputted by the relay apparatus (30).
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 5, 2024
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Hitoshi Hasunuma, Jun Fujimori, Hiroki Kinoshita, Takeshi Yamamoto, Hiroki Takahashi, Kazuki Kurashima
  • Patent number: 10964632
    Abstract: According to one embodiment, there is provided a semiconductor device including a substrate, a semiconductor chip, and a conductive film. The substrate has a main face. The semiconductor chip has a surface equipped with an SRAM circuit. The semiconductor chip is mounted on the main face via a plurality of bump electrodes in a state where the surface faces the main face. The conductive film is disposed on the main face or the surface. The conductive film extends planarly between the plurality of bump electrodes. A region in the main face or the surface where the conductive film is disposed overlaps the SRAM circuit in a direction perpendicular to the main face.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Fujimori, Soichiro Ibaraki, Shinji Yamashita
  • Publication number: 20210061189
    Abstract: The present invention provides an emblem and a cover body of a module capable of suppressing light emission unevenness of an emblem body with a simple configuration. Emblem (20) includes emblem body (32) which includes a transmitting body (42) of which at least a portion has transmittance and non-transmitting body (43) which is a separate body from the transmitting body (42) and does not have the transmittance. Emblem (20) includes light source section (31) disposed between emblem body (32) and cover main body portion (19). Non-transmitting body (43) includes pin (51) which is inserted into opening portion (28) formed in the cover main body portion (19). Pin (51) is held on a rear surface side of cover main body portion (19), and thus, transmitting body (42) and light source section (31) are attached to cover main body portion (19) by non-transmitting body (43).
    Type: Application
    Filed: August 24, 2020
    Publication date: March 4, 2021
    Inventors: Takeshi Fujimori, Yohei Kiuchi
  • Publication number: 20200303290
    Abstract: According to one embodiment, there is provided a semiconductor device including a substrate, a semiconductor chip, and a conductive film. The substrate has a main face. The semiconductor chip has a surface equipped with an SRAM circuit. The semiconductor chip is mounted on the main face via a plurality of bump electrodes in a state where the surface faces the main face. The conductive film is disposed on the main face or the surface. The conductive film extends planarly between the plurality of bump electrodes. A region in the main face or the surface where the conductive film is disposed overlaps the SRAM circuit in a direction perpendicular to the main face.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takeshi FUJIMORI, Soichiro IBARAKI, Shinji YAMASHITA
  • Patent number: 10650876
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element including first and second magnetic layers, and a nonmagnetic layer between the first and the second magnetic layers and capable of setting one of a first state in which magnetization directions of the first and second magnetic layers are parallel and a second state in which magnetization directions of the first and second magnetic layers are antiparallel, and a write circuit that applies a first voltage to the element when setting one of the first and second states to the element and applies a second voltage in a same direction as the first voltage and greater than the first voltage to the element when setting the other one of the first and second states to the element.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Fujimori
  • Patent number: 10644225
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Fujimori
  • Patent number: 10562658
    Abstract: According to an embodiment, a magnetic shield tray includes a main body with a plate form including a magnetic material, and mount portions as holes disposed in the main body. The magnetic material is exposed on an inner surface of the holes.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Fujimori
  • Publication number: 20190279700
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element including first and second magnetic layers, and a nonmagnetic layer between the first and the second magnetic layers and capable of setting one of a first state in which magnetization directions of the first and second magnetic layers are parallel and a second state in which magnetization directions of the first and second magnetic layers are antiparallel, and a write circuit that applies a first voltage to the element when setting one of the first and second states to the element and applies a second voltage in a same direction as the first voltage and greater than the first voltage to the element when setting the other one of the first and second states to the element.
    Type: Application
    Filed: September 7, 2018
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi FUJIMORI
  • Publication number: 20180079547
    Abstract: According to an embodiment, a magnetic shield tray includes a main body with a plate form including a magnetic material, and mount portions as holes disposed in the main body. The magnetic material is exposed on an inner surface of the holes.
    Type: Application
    Filed: December 1, 2017
    Publication date: March 22, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi FUJIMORI
  • Publication number: 20180006212
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi FUJIMORI
  • Publication number: 20160276578
    Abstract: According to one embodiment, a device including a magnetoresistive element is disclosed. The device includes a substrate, a second layer provided on the substrate and including a magnetic material, and a third layer provided on a top or bottom of the second layer and including a material having a negative coefficient of thermal expansion.
    Type: Application
    Filed: June 4, 2015
    Publication date: September 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KOBAYASHI, Kenji NOMA, Takeshi FUJIMORI
  • Patent number: 9349942
    Abstract: A semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 24, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi Fujimori
  • Publication number: 20160111630
    Abstract: A semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi FUJIMORI
  • Patent number: 9252108
    Abstract: According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: February 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi Fujimori
  • Publication number: 20150084141
    Abstract: According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.
    Type: Application
    Filed: December 24, 2013
    Publication date: March 26, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi FUJIMORI
  • Patent number: 8749527
    Abstract: An input device includes a transparent display panel configured to display a graphical interface, an input plate disposed above the display panel and composed of a material that transmits the graphical interface and allows infrared light to propagate through the input plate, an infrared-emitting unit disposed in contact with the input plate and configured to emit the infrared light into the input plate via a contact surface of the input plate, and an infrared detection unit disposed below the input plate and configured to detect diffused light of the infrared light which is generated at the input plate when the input plate is touched.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: June 10, 2014
    Assignees: University of Tsukuba, CYBERDYNE Inc.
    Inventors: Damien Douxchamps, Takeshi Fujimori, Yoshiyuki Sankai
  • Publication number: 20120032926
    Abstract: An input device includes a transparent display panel configured to display a graphical interface, an input plate disposed above the display panel and composed of a material that transmits the graphical interface and allows infrared light to propagate through the input plate, an infrared-emitting unit disposed in contact with the input plate and configured to emit the infrared light into the input plate via a contact surface of the input plate, and an infrared detection unit disposed below the input plate and configured to detect diffused light of the infrared light which is generated at the input plate when the input plate is touched.
    Type: Application
    Filed: March 19, 2010
    Publication date: February 9, 2012
    Inventors: Damien Douxchamps, Takeshi Fujimori, Yoshiyuki Sankai
  • Patent number: 7882764
    Abstract: A steering wheel includes (a) a core member having a boss portion, a spoke portion, and a rim portion, the spoke portion stretching between the boss portion and the rim portion; and (b) a polyurethane member covering at least the rim portion of the core member, the polyurethane member having a specific gravity of 0.7 to 0.9 and a Shore A hardness of 45 to 60. A steering wheel proper defined as being a combination of the core member and the polyurethane member has a weight of 1.0 to 2.5 kg. This steering wheel is satisfied in both of weight reduction and maintenance of moment of inertia necessary for steering wheel.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: February 8, 2011
    Assignee: Nihon Plast Co., Ltd.
    Inventors: Shuji Yamada, Takashi Tokita, Takeshi Fujimori