Patents by Inventor Takeshi Fukami
Takeshi Fukami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9553067Abstract: A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.Type: GrantFiled: August 4, 2014Date of Patent: January 24, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takeshi Fukami
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Publication number: 20160284660Abstract: A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the semiconductor layer, and a solder layer being in contact with the electrode layer and the crack starting point layer. A joining force between the solder layer and the crack starting point layer is smaller than a joining force between the solder layer and the electrode layer.Type: ApplicationFiled: August 4, 2014Publication date: September 29, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takeshi Fukami
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Patent number: 9224698Abstract: A semiconductor device 1 is provided with a semiconductor substrate 10, an electrode 30 formed on a surface of the semiconductor substrate 10, and an insulation film 20 formed on the electrode 30. The semiconductor device 1 includes a metal film 40 extending over a part of the surface of the electrode 30 not covered by the insulation film 20 and a surface of the insulation film 20. The semiconductor device 1 includes solder 80 formed on a surface of the metal film 40, a lead frame 50 joined to the metal film 40 by the solder 80, and sealing resin 60 sealing the insulation film 20, the metal film 40, and the solder 80. A convex 70 is formed on the surface of the insulation film 20. The metal film 40 covers the convex 70. The solder 80 covers the metal film 40 covering the convex 70.Type: GrantFiled: April 15, 2015Date of Patent: December 29, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Takeshi Fukami
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Publication number: 20150357289Abstract: A semiconductor device 1 is provided with a semiconductor substrate 10, an electrode 30 formed on a surface of the semiconductor substrate 10, and an insulation film 20 formed on the electrode 30. The semiconductor device 1 includes a metal film 40 extending over a part of the surface of the electrode 30 not covered by the insulation film 20 and a surface of the insulation film 20. The semiconductor device 1 includes solder 80 formed on a surface of the metal film 40, a lead frame 50 joined to the metal film 40 by the solder 80, and sealing resin 60 sealing the insulation film 20, the metal film 40, and the solder 80. A convex 70 is formed on the surface of the insulation film 20. The metal film 40 covers the convex 70. The solder 80 covers the metal film 40 covering the convex 70.Type: ApplicationFiled: April 15, 2015Publication date: December 10, 2015Inventor: Takeshi FUKAMI
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Patent number: 8755185Abstract: A semiconductor module includes an upper arm and a lower arm of an inverter circuit. The upper arm has a switching element and a rectifying device and the lower arm has a switching element and a rectifying device. The upper arm and the lower arm are laminated such that the switching elements overlap each other and the rectifying devices overlap each other. Refrigerant flow paths constituting cooling sections respectively extend along both sides in the lamination direction of the switching elements and the rectifying devices and are folded back at the rectifying device lamination section side.Type: GrantFiled: January 8, 2010Date of Patent: June 17, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventors: Chung-chih Chou, Takeshi Fukami, Yuji Oda
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Publication number: 20120250253Abstract: A semiconductor module includes an upper arm and a lower arm of an inverter circuit. The upper arm has a switching element and a rectifying device and the lower arm has a switching element and a rectifying device. The upper arm and the lower arm are laminated such that the switching elements overlap each other and the rectifying devices overlap each other. Refrigerant flow paths constituting cooling sections respectively extend along both sides in the lamination direction of the switching elements and the rectifying devices and are folded back at the rectifying device lamination section side.Type: ApplicationFiled: January 8, 2010Publication date: October 4, 2012Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Chung-chih Chou, Takeshi Fukami, Yuji Oda
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Patent number: 5954629Abstract: Sensors are provided for detecting brain waves of a user, and a band-pass filter is provided for extracting a particular brain waves including an .alpha. wave included in a detected brain wave. The band-pass filter comprises a first band-pass filter having a narrow pass band, and a second band-pass filter having a wide pass band. One of the first and second band-pass filters is selected, and a stimulation signal is produced in dependency on an .alpha. wave extracted by a selected band-pass filter. In accordance with the stimulation signal, a stimulation light is emitted to the user in order to induce the user to relax or sleeping state.Type: GrantFiled: January 31, 1997Date of Patent: September 21, 1999Assignee: Pioneer Electronic CorporationInventors: Masatoshi Yanagidaira, Yuichi Kimikawa, Takeshi Fukami, Mitsuo Yasushi
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Patent number: 5031181Abstract: An error correcting apparatus including a circuit for detecting error correcting modes of incoming digital information, a generator for generating a first set of syndromes for a first error correcting mode when the incoming digital information is detected as the first error correcting mode, a generator for generating a second set of syndromes for a second error correcting mode when the incoming digital information is detected as the second error correcting mode, a generator for generating quasi-syndromes for the second error correcting mode by adding an additional syndrome to the syndromes for the first error correcting mode when the incoming digital information is detected as the first error correcting mode, and an error correction circuit for applying an error correcting process to the incoming digital information based on the generated syndromes for the second error correcting mode in spite of the error correcting modes of the incoming digital information.Type: GrantFiled: July 27, 1989Date of Patent: July 9, 1991Assignee: Sony CorporationInventors: Yoichiro Sako, Shigeru Imura, Takeshi Fukami
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Patent number: 4876719Abstract: A synchronizing system for use with a plurality of digital signal reproducers includes a plurality of digital signal reproducers, each having a digital I/O modulator, a digital I/O demodulator and a decoder; a digital signal multiplexer supplied with the output signal from the plurality of digital signal reproducers, and for producing a frame synchronizing signal, a plural channel of digital signals; the digital signal multiplexer including a clock pulse generator, a word synchronizing signal generator, a digital I/O modulator and a digital I/O demodulator. The corresponding digital I/O modulator and digital I/O demodulator are coupled to each other so as to synchronize the plurality of digital signal reproducers.Type: GrantFiled: April 10, 1987Date of Patent: October 24, 1989Assignee: Sony CorporationInventors: Taro Nakagami, Takeshi Fukami, Toshiro Terauchi
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Patent number: 4787085Abstract: A digital signal transmitting system includes a plurality of digital signal reproducers, each outputting a digital data signal to be time-division multiplexed; a digital signal multiplexer supplied with a frame synchronizing signal, a service bit signal and the output digital signals from the reproducers and for producing a block data signal including the frame synchronizing signal, the service bit signal and a plurality of slot data bits arranged with the digital data signals, each one bit within a multiple-frame, in which the service bit signal is indicative of the transmission mode and the slot data associated with each of the plurality of digital data signals being transmitted.Type: GrantFiled: May 29, 1987Date of Patent: November 22, 1988Assignees: Nippon Telegraph and Telephone Corporation, Sony CorporationInventors: Kohichi Suto, Hisayoshi Sugiyama, Akira Sakamoto, Takeshi Fukami, Toshiro Terauchi, Masakatsu Toyoshima
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Patent number: 4683586Abstract: A scrambling system for an audio frequency signal is disclosed which employs a timebase-compressing and/or expanding system to measure the compressed and/or expanded amount of a segment time length caused in a transmission recording and reproducing system. In the scrambling system of the present invention, a marker signal is inserted into a portion between the adjoining segments and transmitted from an encoder side to a decoder side, while at the decoder side, this marker signal is detected, the synchronization is achieved by this marker signal along the compression and expansion of the segment length and the respective segments are rearranged to the original correct order. Thus, the connected portion between the segments can be made smooth so that it is possible to obtain the scrambling system for an audio frequency signal having high accuracy and high reliability.Type: GrantFiled: December 29, 1983Date of Patent: July 28, 1987Assignee: Sony CorporationInventors: Akira Sakamoto, Takeshi Fukami, Takehiro Sugita, Masakatsu Toyoshima
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Patent number: 4612627Abstract: A digital signal composing circuit includes a first selector for selecting a plurality of digital data, a second selector for selecting one of the digital data and a feedback signal, a control circuit for controlling the switching of the first and second selectors and an adding circuit for adding outputs of the first and second selectors and supplying the added output to the second selector as the feedback signal wherein the final output is derived from the adding circuit. Thus, without using any multiplier, the signal processing can be widely used in the digital signal processing such as digital volume, cross-fade, fade-in/-out, mixing, linear interpolation and the like.Type: GrantFiled: December 13, 1983Date of Patent: September 16, 1986Assignee: Sony CorporationInventors: Takehiro Sugita, Akira Sakamoto, Takeshi Fukami, Michimasa Komatsubara, Akira Shimizu
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Patent number: 4600941Abstract: A scrambling system for an audio frequency signal in which an audio signal is divided into blocks, each block being formed of a plurality of frames, the plurality of frames are rearranged on a timebase in a predetermined order at every block so as to be encoded and the encoded signal is re-arranged on the timebase in an original order so as to be decoded, in which there are provided a first signal processing circuit for inserting a redundant portion into a portion between adjoining frames and timebase-compressing the frames in response to the redundant portions upon encoding, a control signal generating circuit for inserting a control signal other than an audio information into the redundant portions, a control signal detecting circuit for detecting the control signal upon decoding and a second signal processing circuit for removing the redundant portions in synchronism with the detected control signal and timebase-expanding the frames in response to the redundant portions.Type: GrantFiled: December 13, 1983Date of Patent: July 15, 1986Assignee: Sony CorporationInventors: Akira Sakamoto, Toshihiko Waku, Takeshi Fukami, Masakatsu Toyoshima, Michimasa Komatsubara
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Patent number: 4598169Abstract: A system for detecting a marker signal with a predetermined pattern inserted periodically in an information signal comprises a circuit which repetitively generates window signals and successively shifts the window signals in a step-wise fashion during a predetermined interval, a detecting circuit which employs the window signals to detect at least a portion of a marker signal in the information signal when at least the portion of the detected marker signal occurs during one of the window signals, a circuit which determines when the detected marker signal has the predetermined pattern to generate a net marker signal in response thereto, and a circuit responsive to the net marker signal which repetitively generates subsequent unshifted window signals beginning a predetermined time after the detected marker signal.Type: GrantFiled: December 21, 1983Date of Patent: July 1, 1986Assignee: Sony CorporationInventors: Michimasa Komatsubara, Takeshi Fukami, Akira Sakamoto, Takehiro Sugita, Toshiya Miyata
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Patent number: 4134076Abstract: A pulse width modulated signal amplifier includes an integrator having a positive or non-inverted input terminal supplied with a modulating signal, such as, an audio signal, and an inverted input terminal supplied with a rectangular wave signal as a carrier, a high gain amplifier receiving the output of the integrator and producing a pulse width modulated signal, a pulse power amplifier receiving the pulse width modulated signal, a low pass filter receiving the output of the pulse power amplifier and producing an amplified demodulated signal corresponding to the original modulating signal and which is supplied to an output terminal, and a negative feedback circuit connected between the output terminal of the pulse power amplifier and the inverted input terminal of the integrator.Type: GrantFiled: December 2, 1977Date of Patent: January 9, 1979Assignee: Sony CorporationInventors: Tadao Suzuki, Takeshi Fukami