Abstract: According to one embodiment, a semiconductor memory device includes memory cells storing data based on respective threshold voltages, having a positive threshold voltage in a data erased state, and includes respective control electrodes. Word lines are selectively electrically connected to the control electrodes of the memory cells, and charged to a potential before writing data to the memory cells. A voltage generator outputs a voltage at an output and includes a first path which discharges the output. A connection circuit is selectively electrically connected to the output of the voltage generator and a first word line, and selectively electrically connects the first word line to a first node which supplies a potential.

Abstract: A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

Abstract: According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.

Abstract: A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being

Abstract: According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.

Abstract: In a booster, a first transistor of a second conduction-type is formed on a first conduction-type substrate and connected to between a voltage-source and an output so that the first transistor functions as a diode. A first capacitor is connected to a first node of the first transistor on a voltage-source side, and transmits a first clock to the first node. A second transistor of the first conduction-type is connected to a second node of the first transistor on an output side to receive the first clock. A second capacitor is connected to the second node and transmits a second clock having an opposite phase of the first clock to the second node. The first transistor transfers the first node's voltage stepped up by the first clock to the second node. The second transistor transfers the second node's voltage stepped up by the second clock to an output side.

Abstract: A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being