Abstract: The present invention further provides a composition for inhibiting purine body absorption, a composition for inhibiting purine nucleotide metabolism, a composition for inhibiting phosphatase, a composition for inhibiting uric acid level elevation, a composition for improving blood pressure, a composition for improving blood glucose level, a composition for improving liver function, a composition for controlling serum iron level, or a composition for promoting calcium absorption, comprising an inositol phosphate or a salt thereof. The present invention further provides a composition comprising an inositol phosphate or a salt thereof, wherein the taste thereof is improved by adding thereto a predetermined amount of calcium lactate.

Abstract: The present invention further provides a composition for inhibiting purine body absorption, a composition for inhibiting purine nucleotide metabolism, a composition for inhibiting phosphatase, a composition for inhibiting uric acid level elevation, a composition for improving blood pressure, a composition for improving blood glucose level, a composition for improving liver function, a composition for controlling serum iron level, or a composition for promoting calcium absorption, comprising an inositol phosphate or a salt thereof. The present invention further provides a composition comprising an inositol phosphate or a salt thereof, wherein the taste thereof is improved by adding thereto a predetermined amount of calcium lactate.

Abstract: The present invention further provides a composition for inhibiting purine body absorption, a composition for inhibiting purine nucleotide metabolism, a composition for inhibiting phosphatase, a composition for inhibiting uric acid level elevation, a composition for improving blood pressure, a composition for improving blood glucose level, a composition for improving liver function, a composition for controlling serum iron level, or a composition for promoting calcium absorption, comprising an inositol phosphate or a salt thereof. The present invention further provides a composition comprising an inositol phosphate or a salt thereof, wherein the taste thereof is improved by adding thereto a predetermined amount of calcium lactate.

Abstract: A major object of the present invention is to provide an effective means for promoting polyamine synthesis in an organism (in particular, in humans). Lactobacillus paracasei having polyamine production promoting activity in an organism.

Abstract: A major object of the present invention is to provide an effective means for promoting polyamine synthesis in an organism (in particular, in humans). Lactobacillus paracasei having polyamine production promoting activity in an organism.

Abstract: The bit strings of multipliers B and N are converted through the use of the Booth's algorithm in units composed of a predetermined number of bits and the operation of A×B+u×N is executed by a carry save adder using the value of an integral multiple of multiplicand A corresponding to the multiplication result of the values of the converted multiplier B and multiplicand A and also the value of an integral multiple of multiplicand u corresponding to the multiplication result of the values of the converted multiplier N and multiplicand u. The operation result of A×B+u×N supplied from the carry save adder are added to the operation result in the past of A×B+u×N through the use of an adder and the added result is supplied as the result of a modular-multiplication operation S=S+A×B+u×N.

Abstract: Either a multiplicand A or 0 is selected, depending on the value of multiplier B supplied in a unit composed of q bits through the use of selectors, and the selected result is provided, and either a multiplicand u or 0 is selected, depending on the value of multiplier N supplied in a unit composed of q bits through the use of selectors, and the selected result is provided. A carry save adder implements the operation of A×B+u×N making use of the values successively supplied from the selectors. To the operation result of A×B+u×N supplied from the carry save adder in a unit composed of q bits is added the operation result of A×B+u×N in the past supplied in a unit composed of q bits and the added result is issued as a result of the modular-multiplication operation S.

Abstract: A two-dimensional PE (processing element) array that can achieve a small amount of hardware, short transfer time and high flexibility. It includes q.times.r CAMs, where q and r are any integers equal to or greater than two, and hit-flag lines. Each CAM has one-dimensionally arrayed w words, a hit-flag register capable of shift up and shift down, and an upper shift I/O port and a lower shift I/O port for inputting from and outputting to outside the contents of the hit-flag register. Each of the hit-flag lines connects the lower-shift I/O port of one of two horizontally adjacent CAMs with the upper-shift I/O port of the other of the two. The w words are arranged in m rows and n columns and are connected in a zigzag, and each word is assigned to a PE that performs various types of logical and arithmetic operations.

Abstract: A two-dimensional PE (processing element) array that can achieve a small amount of hardware, short transfer time and high flexibility. It includes q.times.r CAMs, where q and r are any integers equal to or greater than two, and hit-flag lines. Each CAM has one-dimensionally arrayed w words, a hit-flag register capable of shift up and shift down, and an upper shift I/O port and a lower shift I/O port for inputting from and outputting to outside the contents of the hit-flag register. Each of the hit-flag lines connects the lower-shift I/O port of one of two horizontally adjacent CAMs with the upper-shift I/O port of the other of the two. The w words are arranged in m rows and n columns and are connected in a zigzag, and each word is assigned to a PE that performs various types of logical and arithmetic operations.

Abstract: A built-in self test circuit includes a pattern generator, a functional block subjected to a self test on the basis of an output from the pattern generator, a space compressor for compressing a test result of the functional block, and a comparator for comparing an output from the space compressor with an expected value and outputting a comparison result. The functional block has O (positive integer) inputs and M (positive integer) outputs. The pattern generator is constituted by a linear feedback shift register, having an output bit width P (P=O/N) which is 1/N of the inputs O of the functional block, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from the linear feedback shift register in units of N outputs and outputting, to the functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from the linear feedback shift register every P bits.