Patents by Inventor Takeshi Kagawa

Takeshi Kagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020738
    Abstract: A capacitor having a substrate, a first electrode layer, a dielectric layer, a second electrode layer, and first and second outer electrodes. The substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode layer is on the first main surface of the substrate. The dielectric layer is on at least part of the first electrode layer. The second electrode layer is on at least part of the dielectric layer. The first outer electrode is electrically connected to the first electrode layer and the second outer electrode is electrically connected to the second electrode layer. At least one of the first electrode layer and the first outer electrode and the second electrode layer and the second outer electrode are in contact with each other at a first contact surface. The first contact surface includes a first uneven surface portion.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Inventors: Takeshi Kagawa, Masatomi Harada
  • Publication number: 20200082989
    Abstract: A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Hiroshi Matsubara, Nubuhiro Ishida
  • Publication number: 20190311854
    Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
  • Publication number: 20190244762
    Abstract: A capacitor that includes a substrate having a first principal surface, a second principal surface facing the first principal surface, and a first end surface connecting the first principal surface and the second principal surface, a lower electrode on the first principal surface of the substrate, a dielectric film on the lower electrode, an upper electrode on the dielectric film, a protective film covering the upper electrode and having a thickness smaller than that of the substrate, and a first terminal electrode on the first end surface and electrically connected to one of the upper electrode and the lower electrode.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
  • Publication number: 20190244761
    Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Nobuhiro Ishida
  • Publication number: 20190122820
    Abstract: A capacitor that prevents generation of a substrate capacitance composed of an upper electrode, a substrate, and a lower electrode. Specifically, the capacitor includes a substrate; a lower electrode disposed on the substrate; a dielectric film disposed on the lower electrode; an upper electrode disposed on a part of the dielectric film; and a first terminal electrode that is connected to the upper electrode. Moreover, the upper electrode and the first terminal electrode are formed in a region for forming the lower electrode in a plan view of the capacitor viewed from the first terminal electrode side.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Nobuhiro Ishida
  • Publication number: 20190074348
    Abstract: A capacitor that includes a substrate; a lower electrode formed on the substrate, and including an upper surface, a lower surface and an end surface that connects the upper surface and the lower surface. Moreover, the capacitor includes a dielectric film formed on the lower electrode; an upper electrode formed on the dielectric film; and a terminal electrode connected to the upper electrode. Furthermore, the upper surface of the lower electrode is formed in a region on an inner side of a periphery of the lower surface of the lower electrode with at least part of the end surface being a tapered shape.
    Type: Application
    Filed: November 5, 2018
    Publication date: March 7, 2019
    Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
  • Patent number: 9235114
    Abstract: A reflective mask includes a substrate and a multilayer reflective film formed on the substrate. An absorption pattern is formed on the multilayer reflective film. A recess is formed in the multilayer reflective film in a peripheral region of the absorption pattern.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 12, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takeshi Kagawa
  • Patent number: 8865588
    Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takeshi Kagawa
  • Publication number: 20140127613
    Abstract: A reflective mask includes a substrate and a multilayer reflective film formed on the substrate. An absorption pattern is formed on the multilayer reflective film. A recess is formed in the multilayer reflective film in a peripheral region of the absorption pattern.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 8, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takeshi Kagawa
  • Publication number: 20140113441
    Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
    Type: Application
    Filed: December 24, 2013
    Publication date: April 24, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takeshi Kagawa
  • Patent number: 8642464
    Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: February 4, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takeshi Kagawa
  • Publication number: 20130065389
    Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
    Type: Application
    Filed: July 31, 2012
    Publication date: March 14, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takeshi Kagawa
  • Patent number: D669583
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: October 23, 2012
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa
  • Patent number: D670392
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: November 6, 2012
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa
  • Patent number: D699854
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: February 18, 2014
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa
  • Patent number: D736929
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: August 18, 2015
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa
  • Patent number: D751717
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 15, 2016
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa
  • Patent number: D760915
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 5, 2016
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa
  • Patent number: D768313
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 4, 2016
    Assignee: Nakanishi Inc.
    Inventor: Takeshi Kagawa