Patents by Inventor Takeshi Kamikawa

Takeshi Kamikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12146237
    Abstract: A method for obtaining a smooth surface of an epi-layer with epitaxial lateral overgrowth. The method does not use mis-cut orientations and does not suppress the occurrence of pyramidal hillocks, but instead embeds the pyramidal hillocks in the epi-layer. A growth restrict mask is used to limit the expansion of the pyramidal hillocks in a lateral direction. The surface of the epi-layer becomes extremely smooth due to the disappearance of the pyramidal hillocks.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 19, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Takeshi Kamikawa, Srinivas Gandrothula
  • Publication number: 20240348003
    Abstract: A manufacturing method for a semiconductor device includes a step of preparing a main substrate, a base semiconductor part formed above the main substrate, and a compound semiconductor part formed on the base semiconductor part, and a step of isolating the base semiconductor part and the compound semiconductor part with a cavity surface formed at least in the compound semiconductor part, and isolating the base semiconductor part and the compound semiconductor part into multiple element portions.
    Type: Application
    Filed: July 27, 2022
    Publication date: October 17, 2024
    Applicant: KYOCERA CORPORATION
    Inventors: Kentaro MURAKAWA, Takeshi KAMIKAWA, Yoshinobu KAWAGUCHI
  • Publication number: 20240322078
    Abstract: A semiconductor substrate includes a base substrate, a mask layer including an opening portion and a mask portion, and a GaN-based semiconductor layer that includes a GaN-based semiconductor. The GaN-based semiconductor layer includes: a first portion located on the mask portion; and a second portion that is located on the opening portion and has a lower dislocation density of non-threading dislocations in a cross section of the GaN-based semiconductor layer taken along a thickness direction than the first portion.
    Type: Application
    Filed: December 28, 2021
    Publication date: September 26, 2024
    Applicant: KYOCERA Corporation
    Inventors: Takeshi KAMIKAWA, Katsuaki MASAKI, Yuichiro HAYASHI, Toshihiro KOBAYASHI
  • Publication number: 20240313151
    Abstract: A manufacturing method of a semiconductor device includes a step of preparing a template substrate including a main substrate and a mask pattern located above the main substrate and including a mask portion and an opening portion, a step of forming a first semiconductor part on the mask pattern by using an ELO method, a step of removing a portion of the main substrate overlapping the opening portion in plan view; and, a step of removing a portion of the first semiconductor part overlapping the opening portion in plan view.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 19, 2024
    Applicant: KYOCERA Corporation
    Inventors: Kentaro MURAKAWA, Takeshi KAMIKAWA
  • Patent number: 12087577
    Abstract: A method for dividing a bar of one or more devices. The bar is comprised of island-like III-nitride-based semiconductor layers grown on a substrate using a growth restrict mask; the island-like III-nitride-based semiconductor layers are removed from the substrate using an Epitaxial Lateral Overgrowth (ELO) method; and then the bar is divided into the one or more devices using a cleaving method.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 10, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Takeshi Kamikawa, Srinivas Gandrothula
  • Publication number: 20240283219
    Abstract: A semiconductor laser body includes a base semiconductor part and a compound semiconductor part positioned on the base semiconductor part and containing a GaN-based semiconductor. The base semiconductor part includes a first portion and a second portion having a lower density of threading dislocation extending in a thickness direction than the first portion, the compound semiconductor part includes an optical resonator including a pair of resonant end surfaces, at least one of the pair of resonant end surfaces is an m-plane or a c-plane of the compound semiconductor part, and a resonant length, which is a distance between the pair of resonant end surfaces, is equal to or less than 200 [?m].
    Type: Application
    Filed: June 8, 2022
    Publication date: August 22, 2024
    Applicant: KYOCERA Corporation
    Inventors: Kentaro MURAKAWA, Takeshi KAMIKAWA, Yoshinobu KAWAGUCHI
  • Publication number: 20240275133
    Abstract: A semiconductor device includes a semiconductor substrate including a main substrate, a base semiconductor part located above the main substrate, and a hole penetrating the main substrate in a thickness direction, a compound semiconductor part located above the base semiconductor part, a first light reflector located above the compound semiconductor part, and a second light reflector disposed in the hole, overlapping the first light reflector, and below the first light reflector.
    Type: Application
    Filed: June 13, 2022
    Publication date: August 15, 2024
    Applicant: KYOCERA Corporation
    Inventors: Takeshi KAMIKAWA, Yoshinobu KAWAGUCHI, YuKi TANIGUCHI, Kentaro MURAKAWA
  • Publication number: 20240275132
    Abstract: A semiconductor device includes a base substrate, a first light reflector located above the base substrate, a first mask located above the first light reflector, a base semiconductor part located above the first mask, a compound semiconductor part located above the base semiconductor part, and a second light reflector located above the compound semiconductor part and the first light reflector.
    Type: Application
    Filed: May 27, 2022
    Publication date: August 15, 2024
    Applicant: KYOCERA Corporation
    Inventors: Takeshi KAMIKAWA, Yoshinobu KAWAGUCHI, Yuki TANIGUCHI
  • Patent number: 12051765
    Abstract: An epitaxial lateral overgrowth (ELO) layer is grown on an opening area of a substrate, wherein the ELO layer is higher than a surface 5 of a trench in the substrate. The trench is apt to form a symmetric shape of the ELO layer, which renders it suitable for flip-chip bonding The shape of the ELO layer has a depressed surface region at a back side of a bar formed by the ELO layer. A cleaving point is located higher than the bottom of the ELO layer, so that a force can be efficiently applied to 10 the cleaving point for removing the bar.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: July 30, 2024
    Assignee: THE REGENTS OF THE UNIVERITY OF CALIFORNIA
    Inventors: Takeshi Kamikawa, Srinivas Gandrothula, Masahiro Araki
  • Patent number: 12046695
    Abstract: A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 23, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, Daniel A. Cohen
  • Publication number: 20240234141
    Abstract: A semiconductor substrate includes a support substrate, a mask pattern located above the support substrate and including a mask portion, a seed portion locally located in a layer above the support substrate in a plan view, and a semiconductor part including a GaN-based semiconductor and located above the mask pattern to be in contact with the seed portion and the mask portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Takeshi KAMIKAWA, Toshihiro KOBAYASHI, Yuichiro HAYASHI, Yuta AOKI
  • Publication number: 20240234631
    Abstract: A manufacturing method for a semiconductor device according to the present disclosure includes preparing a laminate body including a plurality of semiconductor layers, and a first support body including an upper surface, a side surface, and a recessed portion including an opening adjacent to the upper surface and the side surface, bonding and disposing the laminate body to the upper surface of the first support body, forming a first end surface at the laminate body, and forming a first dielectric layer on the first end surface.
    Type: Application
    Filed: February 21, 2022
    Publication date: July 11, 2024
    Applicant: KYOCERA Corporation
    Inventors: Yoshinobu KAWAGUCHI, Takeshi KAMIKAWA, Kentaro MURAKAWA
  • Publication number: 20240234137
    Abstract: A template substrate including a first seed region and a growth restricting region that are aligned in a first direction, and a first semiconductor part positioned above the template substrate are provided, the first semiconductor part includes a first base positioned above the first seed region, and a first wing connected to the first base, the first wing facing the growth restricting region with a first void space interposed therebetween, the first wing includes an edge positioned above the growth restricting region, and a ratio of a width of the first void space with respect to a thickness of the first void space in the first direction is equal to or larger than 5.0.
    Type: Application
    Filed: October 19, 2022
    Publication date: July 11, 2024
    Applicant: KYOCERA CORPORATION
    Inventors: Takeshi KAMIKAWA, Yuta AOKI, Kazuma TAKEUCHI, Katsuaki MASAKI, Fumio YAMASHITA
  • Publication number: 20240203732
    Abstract: A main substrate, a seed portion (SD) located higher than the main substrate, and first and second semiconductor parts (8F and 8S) arranged side by side in a first direction (9Y direction) are provided. The first and second semiconductor parts are in contact with the seed portion, a longitudinal direction of the seed portion (SD) is the first direction (Y direction), and a hollow portion (VD) is located between the main substrate (1) and each of the first semiconductor part and the second semiconductor part.
    Type: Application
    Filed: April 14, 2022
    Publication date: June 20, 2024
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Takeshi KAMIKAWA, Toshihiro KOBAYASHI, Yuichiro HAYASHI, Yuki TANIGUCHI, Yuta AOKI
  • Publication number: 20240191391
    Abstract: A semiconductor substrate includes a main substrate, a mask pattern located above the main substrate and including a mask portion, and a first semiconductor part and a second semiconductor part located above the mask pattern and adjacent to each other, in which the first semiconductor part includes a first lower edge located on the mask portion and a first protruding portion protruding toward the second semiconductor part side farther than the first lower edge.
    Type: Application
    Filed: March 30, 2022
    Publication date: June 13, 2024
    Applicant: KYOCERA Corporation
    Inventors: Toshihiro KOBAYASHI, Takeshi KAMIKAWA, Yuta AOKI, Yuichiro HAYASHI
  • Publication number: 20240145622
    Abstract: A template substrate includes: a main substrate including an edge (E), a peripheral portion including the edge, and a non-peripheral portion located on the inner side of the peripheral portion; and a mask pattern located above the main substrate. The mask pattern includes a mask portion, a plurality of first opening portions (KF) each having a width direction as a first direction and a longitudinal direction as a second direction and overlapping the non-peripheral portion in plan view, and one or more second opening portions (KB) arranged along the edge in plan view.
    Type: Application
    Filed: February 22, 2022
    Publication date: May 2, 2024
    Applicant: KYOCERA Corporation
    Inventor: Takeshi KAMIKAWA
  • Publication number: 20240136470
    Abstract: A manufacturing method for a semiconductor device according to the present disclosure includes preparing a laminate body including a plurality of semiconductor layers, and a first support body including an upper surface, a side surface, and a recessed portion including an opening adjacent to the upper surface and the side surface, bonding and disposing the laminate body to the upper surface of the first support body, forming a first end surface at the laminate body, and forming a first dielectric layer on the first end surface.
    Type: Application
    Filed: February 21, 2022
    Publication date: April 25, 2024
    Applicant: KYOCERA Corporation
    Inventors: Yoshinobu KAWAGUCHI, Takeshi KAMIKAWA, Kentaro MURAKAWA
  • Publication number: 20240136177
    Abstract: A template substrate including a first seed region and a growth restricting region that are aligned in a first direction, and a first semiconductor part positioned above the template substrate are provided, the first semiconductor part includes a first base positioned above the first seed region, and a first wing connected to the first base, the first wing facing the growth restricting region with a first void space interposed therebetween, the first wing includes an edge positioned above the growth restricting region, and a ratio of a width of the first void space with respect to a thickness of the first void space in the first direction is equal to or larger than 5.0.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: KYOCERA CORPORATION
    Inventors: Takeshi KAMIKAWA, Yuta AOKI, Kazuma TAKEUCHI, Katsuaki MASAKI, Fumio YAMASHITA
  • Publication number: 20240136181
    Abstract: A semiconductor substrate includes a support substrate, a mask pattern located above the support substrate and including a mask portion, a seed portion locally located in a layer above the support substrate in a plan view, and a semiconductor part including a GaN-based semiconductor and located above the mask pattern to be in contact with the seed portion and the mask portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Applicant: KYOCERA Corporation
    Inventors: Katsuaki MASAKI, Takeshi KAMIKAWA, Toshihiro KOBAYASHI, Yuichiro HAYASHI, Yuta AOKI
  • Publication number: 20240120708
    Abstract: A light-emitting body includes a base semiconductor part including a nitride semiconductor, a compound semiconductor part including a nitride semiconductor and positioned above the base semiconductor part, and a first electrode and a second electrode. The base semiconductor part includes first part and second part having a density of threading dislocation extending in a thickness direction lower than that of the first part, at least part of the first electrode and at least part of the second electrode are positioned on the compound semiconductor part, and at least part of the first electrode is positioned above the second part.
    Type: Application
    Filed: June 13, 2022
    Publication date: April 11, 2024
    Applicant: KYOCERA Corporation
    Inventors: Yoshinobu KAWAGUCHI, Takeshi KAMIKAWA, Kentaro MURAKAWA