Patents by Inventor Takeshi Kataoka
Takeshi Kataoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945984Abstract: A reinforcing film comprises a pressure sensitive adhesive layer laminated and fixed on a principal surface of a film substrate. The pressure sensitive adhesive layer is formed of a photocurable composition containing a photocurable agent and a base polymer having a crosslinked structure. The gel fraction of the photocurable composition is preferably 60% or more. The shear storage elastic modulus at 25° C. of the pressure sensitive adhesive layer is preferably 1×104 to 1.2×105 Pa. The shear storage elastic modulus at 25° C. of the pressure sensitive adhesive layer after photocuring is preferably 1.5×105 to 2×106 Pa.Type: GrantFiled: September 18, 2018Date of Patent: April 2, 2024Assignee: NITTO DENKO CORPORATIONInventors: Takeshi Nakano, Keiji Hayashi, Souya Jo, Shogo Sasaki, Kenichi Kataoka
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Publication number: 20220370533Abstract: An object of the present invention is to provide an intestinal-environment-improving agent. The object can be achieved by an intestinal-environment-improving agent including an acacia bark extract.Type: ApplicationFiled: September 30, 2020Publication date: November 24, 2022Applicants: ACACIA-NO-KI CO., LTD., HOSHI UNIVERSITYInventors: Takeshi KATAOKA, Yasuomi KAWAJI, Sosuke OGAWA, Tomoki KOBAYASHI, Kiyoshi SUGIYAMA, Nobutomo IKARASHI
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Patent number: 8576643Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has a maximum variation width of a threshold voltage for memorizing an information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.Type: GrantFiled: February 8, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 8578135Abstract: A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.Type: GrantFiled: March 16, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Teppei Hirotsu, Yuuichi Abe, Takeshi Kataoka, Yasuhiro Nakatsuka
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Publication number: 20120179953Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.Type: ApplicationFiled: February 8, 2012Publication date: July 12, 2012Inventors: Yutaka SHINAGAWA, Takeshi KATAOKA, Eiichi ISHIKAWA, Toshihiro TANAKA, Kazumasa YANAGISAWA, Kazufumi SUZUKAWA
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Publication number: 20120173850Abstract: A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.Type: ApplicationFiled: March 16, 2012Publication date: July 5, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Teppei HIROTSU, Yuuichi ABE, Takeshi KATAOKA, Yasuhiro NAKATSUKA
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Patent number: 8130571Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: GrantFiled: June 16, 2011Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20110246860Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Inventors: Yutaka SHINAGAWA, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 7998543Abstract: A novel dioxetane compound is provided having a cationically polymerizable oxetane group, which compound is excellent in compatibility with a liquid crystalline compound and a non-liquid crystalline compound. An optical film is also provided with excellent liquid crystal orientation retention properties and mechanical strength, produced by aligning a composition of the dioxetane compound and a cationically polymerizable compound in a liquid crystal orientation and fixing the liquid crystal orientation by polymerization. Further, a liquid crystal display device is provided with the optical film.Type: GrantFiled: October 17, 2006Date of Patent: August 16, 2011Assignee: Nippon Oil CorporationInventors: Takashi Seki, Takeshi Kataoka, Hitoshi Mazaki, Hirofumi Aizono
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Patent number: 7978545Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: GrantFiled: May 6, 2010Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 7821824Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: GrantFiled: October 27, 2008Date of Patent: October 26, 2010Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20100220531Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: May 6, 2010Publication date: September 2, 2010Inventors: YUTAKA SHINAGAWA, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 7752527Abstract: A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.Type: GrantFiled: November 28, 2006Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Hiromichi Yamada, Teppei Hirotsu, Teruaki Sakata, Takeshi Kataoka, Shunichi Iwata
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Patent number: 7581054Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.Type: GrantFiled: July 17, 2007Date of Patent: August 25, 2009Assignee: Renesas Technology Corp.Inventors: Kesami Hagiwara, Takeshi Kataoka, Hisakazu Sato, Shunichi Iwata, Yoshikazu Kiyoshige, Akihiko Tomita
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Publication number: 20090068379Abstract: A novel dioxetane compound is provided having a cationically polymerizable oxetane group, which compound is excellent in compatibility with a liquid crystalline compound and a non-liquid crystalline compound. An optical film is also provided with excellent liquid crystal orientation retention properties and mechanical strength, produced by aligning a composition of the dioxetane compound and a cationically polymerizable compound in a liquid crystal orientation and fixing the liquid crystal orientation by polymerization. Further, a liquid crystal display device is provided with the optical film.Type: ApplicationFiled: October 17, 2006Publication date: March 12, 2009Applicant: NIPPON OIL CORPORATIONInventors: Takashi Seki, Takeshi Kataoka, Hitoshi Mazaki, Hirofumi Aizono
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Publication number: 20090052238Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: October 27, 2008Publication date: February 26, 2009Inventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 7464210Abstract: This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or a hardware interrupt counter for retaining the number of times of occurrence of an interrupt request generation event counts up when a software processing which generates a software interrupt or a hardware event that generates a hardware interrupt occurs, and counts down when a CPU performs a processing for removing the interrupt request. If the value of the software interrupt counter and the value of the hardware interrupt counter are not zero, a software interrupt request signal and a hardware interrupt request signal to the CPU are asserted.Type: GrantFiled: January 19, 2005Date of Patent: December 9, 2008Assignees: Renesas Technology Corp., Denso CorporationInventors: Masafumi Inoue, Takanaga Yamazaki, Takeshi Kataoka, Hideo Kubota, Satoshi Tanaka, Hirokazu Komori, Takahiro Gotoh
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Publication number: 20080046697Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.Type: ApplicationFiled: October 6, 2007Publication date: February 21, 2008Inventors: Yasuo SUGURE, Tomomi ISHIKURA, Kazuya HIRAYANAGI, Takeshi KATAOKA, Seiji TAKEUCHI, Hiromichi YAMADA, Takanaga YAMAZAKI
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Publication number: 20080022030Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.Type: ApplicationFiled: July 17, 2007Publication date: January 24, 2008Inventors: Kesami Hagiwara, Takeshi Kataoka, Hisakazu Sato, Shunichi Iwata, Yoshikazu Kiyoshige, Akihiko Tomita
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Patent number: 7290124Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.Type: GrantFiled: October 23, 2003Date of Patent: October 30, 2007Assignee: Renesas Technology Corp.Inventors: Yasuo Sugure, Tomomi Ishikura, Kazuya Hirayanagi, Takeshi Kataoka, Seiji Takeuchi, Hiromichi Yamada, Takanaga Yamazaki