Patents by Inventor Takeshi Kimura
Takeshi Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12378694Abstract: An object is to improve quality of a nitride crystal. A crystal represented by a composition formula InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, and 0?x+y?1), wherein the concentration of carbon in the crystal is less than 1×1015 cm?3, and the concentration of an electron trap E3 that exits in an energy range from 0.5 eV to 0.65 eV from a lower end of a conduction band in the crystal is less than 1×1014 cm?3.Type: GrantFiled: February 14, 2022Date of Patent: August 5, 2025Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Hajime Fujikura, Takeshi Kimura, Taichiro Konno
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Patent number: 12368594Abstract: Reduce inventory cost without preparing a control device for each destination in advance. This control device is for controlling industrial machinery and includes an encryption unit, and comprises: an encryption device unit that includes a plurality of encryption units corresponding to each of a plurality of destinations, and a plurality of invalidation units that invalidate any one of the plurality of encryption units or invalidate the plurality of encryption units; and an operating unit that, depending on the destination of the control device, selects invalidation of the encryption units by specifying to each of the plurality of invalidation units to invalidate one of the plurality of encryption units or to invalidate the plurality of encryption units.Type: GrantFiled: June 24, 2021Date of Patent: July 22, 2025Assignee: FANUC CORPORATIONInventors: Yumeki Yui, Takeshi Kimura
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Patent number: 12287356Abstract: The voltage hold circuit is a voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit including: a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every the processing cycle.Type: GrantFiled: May 17, 2022Date of Patent: April 29, 2025Assignee: SOCIONEXT INC.Inventors: Kengo Komiya, Akimitsu Tajima, Takeshi Kimura
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Publication number: 20250132151Abstract: To obtain a high-quality semiconductor laminate and a high-quality semiconductor element. [Solution] Provided is a semiconductor laminate including a substrate that includes silicon carbide and has a main surface, a first layer that is provided on the main surface of the substrate and includes an aluminum nitride crystal, a second layer that is provided on the first layer and includes a crystal of any of aluminum gallium nitride, aluminum indium nitride, and aluminum indium gallium nitride, and a third layer that is provided on the second layer and includes a gallium nitride crystal, in which the first layer has tensile strain in a direction along the main surface at 27° C.Type: ApplicationFiled: October 17, 2024Publication date: April 24, 2025Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Hajime FUJIKURA, Fuminasa HORIKIRI, Taichiro KONNO, Takeshi KIMURA, Shota KANEKI
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Patent number: 12225664Abstract: A circuit board assembly includes a first circuit board, a second circuit board having a first side extending adjacent to a first side of the first circuit board, and a metal fitting including a portion bent at the angle and spanning both the first side of the first circuit board and the first side of the second circuit board. The second circuit board is in a posture having an angle other than 180° to the first circuit board. The metal fitting is fixed to both the first circuit board and the second circuit board.Type: GrantFiled: May 18, 2022Date of Patent: February 11, 2025Assignee: TYCO ELECTRONICS JAPAN G.K.Inventors: Daisuke Dobashi, Takeshi Kimura
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Patent number: 12222020Abstract: The present invention relates to a wrapped joined V-belt in which outer peripheral surfaces of a plurality of wrapped V-belt portions are coupled via a tie band, each of the wrapped V-belt portions includes a tension member layer, a tension rubber layer laminated at a belt outer peripheral side, a compression rubber layer laminated at a belt inner peripheral side, and an outside cloth covering an entire outer surface of the belt, and the compression rubber layer includes a first compression rubber layer laminated at the belt outer peripheral side and a second compression rubber layer laminated at the belt inner peripheral side, a rubber hardness of the tension rubber layer is higher than that of the second compression rubber layer, and a rubber hardness of the first compression rubber layer is equal to or higher than that of the tension rubber layer.Type: GrantFiled: May 29, 2019Date of Patent: February 11, 2025Assignee: Mitsuboshi Belting Ltd.Inventors: Takeshi Kimura, Yoshihito Nakaoji
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Publication number: 20240394129Abstract: An information processing device according to one aspect of the present disclosure is capable of safely separating a communication path from a communication port, said information processing device comprising: a communication port that is for connecting a communication path with a communication device; a display unit that displays the state of the communication port; a communication control unit that controls communication with the communication device; a header extraction unit that extracts prescribed header information of communication data; a correspondence storage unit that stores a correspondence between the header information and a risk grade which is preset as a rating indicative of the probability that failure will occur as a result of separation of the communication path from the communication port; a risk determination unit that determines the current risk grade of the communication port on the basis of the correspondence and of the header information extracted by the header extraction unit; and a dType: ApplicationFiled: November 1, 2021Publication date: November 28, 2024Applicant: FANUC CORPORATIONInventor: Takeshi KIMURA
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Patent number: 12125325Abstract: A vehicular apparatus includes a drawer, an input device, functional devices and a maintainer. The drawer executes drawing on a display device. The input device receives a signal indicating an operation for stopping a vehicle. The maintainer maintains the drawer at an operating state to execute drawing required during stopping of the vehicle in response to that the input device receives the signal indicating the operation for stopping the vehicle, and lifts the operating state of the drawer based on a condition that a predetermined ending condition is satisfied.Type: GrantFiled: December 8, 2021Date of Patent: October 22, 2024Assignee: DENSO CORPORATIONInventor: Takeshi Kimura
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Publication number: 20240344931Abstract: An exhaust gas sampling device that collects an exhaust gas emitted from a vehicle including an engine or a part of the vehicle into a sampling bag includes a main channel through which the exhaust gas flows, a main valve that opens and shuts the main channel, a dilution gas channel that is connected downstream from the main valve in the main channel and introduces a dilution gas into the main channel, a purge gas channel that branches from the dilution gas channel and has a downstream end connected downstream from the main valve in the main channel and upstream from a junction of the dilution gas channel and a purge pump that is disposed in the purge gas channel, sucks a part of the dilution gas flowing through the dilution gas channel, and delivers the sucked part as a purge gas to the main channel.Type: ApplicationFiled: October 3, 2022Publication date: October 17, 2024Applicant: HORIBA, LTD.Inventors: Takeshi KIMURA, Kazunori KURIAKI, Masahiro HIGUCHI, Yoji KOMATSU, Jun TOMITA
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Patent number: 12040573Abstract: A connector housing includes a housing main body and a latch arm having a latch arm main body and a latch portion protruding from the latch arm main body. The latch arm main body is formed of a first material, extends like a cantilever from the housing main body, and is elastically deformable with respect to the housing main body. The latch portion is formed of a second material having a higher rigidity than the first material and latches with a latched member. A transition region between the first material and the second material has a continuously changing mixing ratio between the first material and the second material.Type: GrantFiled: April 18, 2022Date of Patent: July 16, 2024Assignee: Tyco Electronics Japan G.K.Inventor: Takeshi Kimura
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Publication number: 20240206342Abstract: There is provided a piezoelectric film, being a polycrystalline film comprised of potassium sodium niobate; containing at least one metal element selected from a group consisting of Cu and Mn; and having 1.0 or less ratio of a concentration B of the metal element at grain boundaries of crystals, with respect to a concentration A of the metal element in a matrix phase of the crystals.Type: ApplicationFiled: February 24, 2021Publication date: June 20, 2024Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Toshiaki KURODA, Kenji SHIBATA, Kazutoshi WATANABE, Takeshi KIMURA
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Patent number: 12011438Abstract: The inventors have found that the compounds of formula (I) protect cardiomyocytes. Accordingly, the disclosure provides a pharmaceutical composition for protecting a cardiomyocyte comprising a compound of formula (I) or an ester, oxide, pharmaceutically acceptable salt or solvate thereof. The pharmaceutical composition may be used for treating or preventing a disease associated with cardiomyocyte death, such as myocardial infarction, chronic heart failure, hypertensive heart failure, or dilated cardiomyopathy, especially for treating myocardial infarction.Type: GrantFiled: April 15, 2019Date of Patent: June 18, 2024Assignee: KYOTO UNIVERSITYInventors: Akira Kakizuka, Koh Ono, Takahiro Horie, Yuya Ide, Naritatsu Saitou, Takeshi Kimura
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Publication number: 20240183024Abstract: There is provided a piezoelectric stack including: a substrate having a main surface with a diameter of 3 inches or more; and a piezoelectric film on the substrate, comprising a perovskite-type alkali niobium oxide containing potassium, sodium, niobium, and oxygen, wherein, a half-value width of an X-ray rocking curve of (001) is within a range of 0.5° or more and 2.5° or less over an entire area of an inside of a main surface of the piezoelectric film excluding its periphery when performing X-ray diffraction measurement on the piezoelectric film.Type: ApplicationFiled: March 3, 2022Publication date: June 6, 2024Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Toshiaki KURODA, Kenji SHIBATA, Kazutoshi WATANABE, Takeshi KIMURA
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Patent number: 12002903Abstract: Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 ?m or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.Type: GrantFiled: November 19, 2020Date of Patent: June 4, 2024Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Hajime Fujikura, Taichiro Konno, Takeshi Kimura
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Publication number: 20240099143Abstract: There is provided a piezoelectric stack including: a substrate (1); a bottom electrode film (2) on the substrate; a piezoelectric film (3) on the bottom electrode film, having a planar area smaller than a planar area of the bottom electrode film; a top electrode film (4) on the piezoelectric film; and an insulating film (5) provided from the top electrode film to the bottom electrode film and covering at least a part of a side surface of the piezoelectric film, wherein the insulating film has a slope (9a) filling a step between a top surface of the top electrode film and a top surface of the bottom electrode film, and the slope has a shape alleviating the step.Type: ApplicationFiled: January 12, 2022Publication date: March 21, 2024Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Toshiaki KURODA, Kenji SHIBATA, Kazutoshi WATANABE, Takeshi KIMURA
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Patent number: 11908902Abstract: Provided is a group III nitride laminate for improving device characteristics, including: an underlying substrate; a first layer that is formed on the underlying substrate and is made of aluminum nitride; and a second layer that is formed on the first layer and is made of gallium nitride, wherein the first layer has a thickness of more than 100 nm and 1 ?m or less, a full width at half maximum of (0002) diffraction determined through X-ray rocking curve analysis is 250 seconds or less, and a full width at half maximum of (10-12) diffraction determined through X-ray rocking curve analysis is 500 seconds or less.Type: GrantFiled: July 7, 2021Date of Patent: February 20, 2024Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Hajime Fujikura, Taichiro Konno, Takeshi Kimura, Osamu Goto
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Publication number: 20230353370Abstract: Reduce inventory cost without preparing a control device for each destination in advance. This control device is for controlling industrial machinery and includes an encryption unit, and comprises: an encryption device unit that includes a plurality of encryption units corresponding to each of a plurality of destinations, and a plurality of invalidation units that invalidate any one of the plurality of encryption units or invalidate the plurality of encryption units; and an operating unit that, depending on the destination of the control device, selects invalidation of the encryption units by specifying to each of the plurality of invalidation units to invalidate one of the plurality of encryption units or to invalidate the plurality of encryption units.Type: ApplicationFiled: June 24, 2021Publication date: November 2, 2023Inventors: Yumeki YUI, Takeshi KIMURA
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Publication number: 20230276711Abstract: There is provided a piezoelectric stack, including: a substrate; an output-side bottom electrode film on the substrate; an output-side piezoelectric film, being an oxide film, on the output-side bottom electrode film; an output-side top electrode film on the output-side piezoelectric film; an input-side bottom electrode film on the substrate; an input-side piezoelectric film, being a nitride film, on the input-side bottom electrode film; an input-side top electrode film on the input-side piezoelectric film; and an ultrasonic output part and ultrasonic input part placed in such a manner as not overlapping each other when viewed from a top surface of the substrate, the ultrasonic output part comprising a stacked part of the output-side bottom electrode film, the output-side piezoelectric film, and the output-side top electrode film, the ultrasonic input part comprising a stacked part of the input-side bottom electrode film, the input-side piezoelectric film, and the input-side top electrode film.Type: ApplicationFiled: February 24, 2021Publication date: August 31, 2023Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Toshiaki KURODA, Kenji SHIBATA, Kazutoshi WATANABE, Takeshi KIMURA
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Publication number: 20230270013Abstract: There is provided a piezoelectric stack, including: a substrate; an oxide film on the substrate, containing zinc and oxygen as main elements; an electrode film on the oxide film; and a piezoelectric film on the electrode film, being an alkali niobium oxide film containing potassium, sodium, niobium, and oxygen and having a perovskite structure.Type: ApplicationFiled: March 16, 2021Publication date: August 24, 2023Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Toshiaki KURODA, Kenji SHIBATA, Kazutoshi WATANABE, Takeshi KIMURA
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Patent number: 11732380Abstract: There is provided a nitride crystal substrate having a main surface and formed of group-III nitride crystal, wherein NIR/NElec, satisfies formula (1) below, which is a ratio of a carrier concentration NIR at a center of the main surface relative to a carrier concentration NElec: 0.5?NIR/NElec?1.5 . . . (1) where NIR is the carrier concentration on the main surface side of the nitride crystal substrate obtained based on a reflectance of the main surface measured by a reflection type Fourier transform infrared spectroscopy, and NElec is the carrier concentration in the nitride crystal substrate obtained based on a specific resistance of the nitride crystal substrate and a mobility of the nitride crystal substrate measured by an eddy current method.Type: GrantFiled: May 13, 2019Date of Patent: August 22, 2023Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Fumimasa Horikiri, Takeshi Kimura