Patents by Inventor Takeshi Kotegawa

Takeshi Kotegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403605
    Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 3, 2019
    Assignee: BUFFALO INC.
    Inventors: Yu Nakase, Takayuki Okinaga, Shuichiro Azuma, Kazuki Makuni, Takeshi Kotegawa, Noriaki Sugahara
  • Publication number: 20180182737
    Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 28, 2018
    Applicant: Buffalo Memory Co, Ltd.
    Inventors: YU NAKASE, Takayuki Okinaga, Shuichiro Azuma, Kazuki Makuni, Takeshi Kotegawa, Noriaki Sugahara