Abstract: There is provided a technique to enable a specific IC chip to reliably activate the other IC chips. An information processing apparatus has first to third IC chips and, after loading an activation program for the third IC chip from a first storage unit connected to the first IC chip into a third storage unit connected to the third IC chip, accesses a register and activates the third control unit.

Abstract: Each of a plurality of IC chips, which are connected in series, is configured such that each IC chip access an entire memory space of each of other IC chips.

Abstract: There is provided a technique to enable a specific IC chip to reliably activate the other IC chips. An information processing apparatus has first to third IC chips and, after loading an activation program for the third IC chip from a first storage unit connected to the first IC chip into a third storage unit connected to the third IC chip, accesses a register and activates the third control unit.

Abstract: Each of a plurality of IC chips, which are connected in series, is configured such that each IC chip access an entire memory space of each of other IC chips.

Abstract: An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the register. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.

Abstract: In an apparatus including a plurality of integrated circuit chips, it makes it possible not to connect a ROM to all integrated circuit chips. Each chip incorporates a processor, and has terminal for connecting with a ROM and a RAM. The chip includes a communication unit communicating with another integrated circuit chip, and a reset controller which includes a register storing initial data setting for the processor in a reset state, and selects, based on a logical level of an external terminal, between whether to provide the data of the register to a reset terminal of the processor and whether to provide an external signal to the reset terminal of the processor.

Abstract: An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the resister. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.

Abstract: In an apparatus including a plurality of integrated circuit chips, it makes it possible not to connect a ROM to all integrated circuit chips. Each chip incorporates a processor, and has terminal for connecting with a ROM and a RAM. The chip includes a communication unit communicating with another integrated circuit chip, and a reset controller which includes a register storing initial data setting for the processor in a reset state, and selects, based on a logical level of an external terminal, between whether to provide the data of the register to a reset terminal of the processor and whether to provide an external signal to the reset terminal of the processor.

Abstract: An image processing apparatus includes a first error diffusion unit, a second error diffusion unit, and a first determining unit, wherein the second error diffusion unit performs error diffusion processing in parallel with the first error diffusion unit and has an operating unit and a calculation unit, and the first determining unit determines whether quantized data for the second pixel of interest is fixed by the second error diffusion unit on the basis of whether the total of value is equal to or lower than a first reference value and whether the total of value is equal to or higher than a second reference value that is higher than the first reference value.

Abstract: An image processing apparatus includes a first error diffusion unit, a second error diffusion unit, and a first determining unit, wherein the second error diffusion unit performs error diffusion processing in parallel with the first error diffusion unit and has an operating unit and a calculation unit, and the first determining unit determines whether quantized data for the second pixel of interest is fixed by the second error diffusion unit on the basis of whether the total of value is equal to or lower than a first reference value and whether the total of value is equal to or higher than a second reference value that is higher than the first reference value.

Abstract: An electronic watermark embedding apparatus and an electronic watermark embedding method can severally deal with both of the resistance property of an electronic watermark and the prevention of image quality deterioration. Electronic watermark information of a high importance level is embedded in a component having a strong resistance property, and electronic watermark information of a low importance level is embedded in a component exerting little influence on an image quality. As a result, the electronic watermark information to be embedded in the component having a strong resistance property is limited to that of a high importance level. Moreover, the image quality deterioration can be suppressed in comparison with the case of embedding all pieces of information, and the electronic watermark information of low importance level is embedded in the component having a weak resistance property but exerting little influence on an image quality.

Abstract: An image processing apparatus, a printing apparatus and an image processing method are provided which can perform quantization processing on image data at high speed based on an error diffusion method while at the same time avoiding degradations in a quality of printed images. When the error value represented by the error data is equal to or less than the reference value, at least a part of the data portion that can represent an error value in excess of the reference value is eliminated to compress the error data.

Abstract: An image processing apparatus, a printing apparatus and an image processing method are provided which can perform quantization processing on image data at high speed based on an error diffusion method while at the same time avoiding degradations in a quality of printed images. When an error value represented by error data is a particular value, the error data is converted into compressed error data with a data volume less than that of the original error data.

Abstract: An oscillator of the present invention includes a constant current circuit in which a constant current generated in the constant current circuit varies positively with an on threshold voltage of a transistor included in the constant circuit; and an oscillating circuit in which the oscillating frequency of a clock signal generated in the oscillating circuit varies positively with the constant current supplied from the constant current circuit, and the oscillating frequency of the clock signal generated in the oscillating circuit varies negatively with an on threshold voltage of a transistor included in the oscillating circuit.

Abstract: An oscillator of the present invention includes a constant current circuit in which a constant current generated in the constant current circuit varies positively with an on threshold voltage of a transistor included in the constant circuit; and an oscillating circuit in which the oscillating frequency of a clock signal generated in the oscillating circuit varies positively with the constant current supplied from the constant current circuit, and the oscillating frequency of the clock signal generated in the oscillating circuit varies negatively with an on threshold voltage of a transistor included in the oscillating circuit.

Abstract: An electronic watermark embedding apparatus and an electronic watermark embedding method can severally deal with both of the resistance property of an electronic watermark and the prevention of image quality deterioration. Electronic watermark information of a high importance level is embedded in a component having a strong resistance property, and electronic watermark information of a low importance level is embedded in a component exerting little influence on an image quality. As a result, the electronic watermark information to be embedded in the component having a strong resistance property is limited to that of a high importance level. Moreover, the image quality deterioration can be suppressed in comparison with the case of embedding all pieces of information, and the electronic watermark information of low importance level is embedded in the component having a weak resistance property but exerting little influence on an image quality.

Abstract: An image processing apparatus, a printing apparatus and an image processing method are provided which can perform quantization processing on image data at high speed based on an error diffusion method while at the same time avoiding degradations in a quality of printed images. When an error value represented by error data is a particular value, the error data is converted into compressed error data with a data volume less than that of the original error data.

Abstract: An image processing apparatus, a printing apparatus and an image processing method are provided which can perform quantization processing on image data at high speed based on an error diffusion method while at the same time avoiding degradations in a quality of printed images. When the error value represented by the error data is equal to or less than the reference value, at least a part of the data portion that can represent an error value in excess of the reference value is eliminated to compress the error data.

Abstract: The invention is to provide an image forming apparatus, for printing an image based on image data, capable of deleting data unnecessary for the user, thereby effectively utilizing limited memory area. The invention provides an image forming apparatus for printing an image based on image data, including a memory unit for memorizing the image data; a determination unit for determining a category of the image data; and a selection unit for selecting whether to erase or to store the image data after being printed, according to a result of determination by the determination unit.

Abstract: There is provided an image processing system in which a management server, a host computer, and a printer are connected via a network, and said host computer prints image data received from said management server based on a printing parameter indicating a printing condition set by a user using said printer, wherein said host computer receives image data appended with a visible digital watermark from said management server, detects a printing parameter set in said printer, collates the detected printing parameter with a limited parameter which is set in advance for the image data, and removes the visible digital watermark from the image data in accordance with the collation result.