Abstract: A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Abstract: A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Abstract: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Abstract: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Abstract: A signal detection device according to the embodiment of the present invention includes a memory and processing circuitry. The memory is configured to store a program. The processing circuitry is for executing the program and is configured to calculate a first signal level indicative of a signal level of a digital complex signal; calculate a first variation indicative of a temporal variation of the first signal level; calculate a statistic in a predetermined first time period on the basis of the first variation within the first time period; and determine, on the basis of the statistic in the first time period, whether or not an interference source signal indicative of a signal of a radio wave coming from an interference source is included in the digital complex signals within the first time period.

Abstract: A signal detection device according to the embodiment of the present invention includes a memory and processing circuitry. The memory is configured to store a program. The processing circuitry is for executing the program and is configured to calculate a first signal level indicative of a signal level of a digital complex signal; calculate a first variation indicative of a temporal variation of the first signal level; calculate a statistic in a predetermined first time period on the basis of the first variation within the first time period; and determine, on the basis of the statistic in the first time period, whether or not an interference source signal indicative of a signal of a radio wave coming from an interference source is included in the digital complex signals within the first time period.

Abstract: In one embodiment, there is provided an amplification circuit. The amplification circuit includes: a plurality of amplifiers configured to amplify an input signal and output the amplified signal; a control circuit configured to control a current supplied to each of the plurality of amplifiers; and a switching circuit configured to switch the amplified signal output from the plurality of amplifiers in response to current control performed by the control circuit.

Abstract: According , one embodiment, a power supply control module includes: a memory module; power supply controller; a voltage determination module; and reset execution module. The power supply controller performs supply/cutoff control of a voltage from a main power supply to a load via a power supply circuit by performing ON/OFF control of a switch module. The voltage determination module determines whether, during a standby state operating on a voltage supplied from a charge accumulating module, a value of the voltage supplied from the charge accumulating module is equal to or smaller than a reset threshold value set in advance. The reset execution module performs a reset execution operation for clearing a status retained in a memory module, the voltage determination module determines that the value of the voltage is equal to or smaller than the reset threshold value.

Abstract: According to an aspect of the invention, a power controller includes: a latching relay module configured to be connected to an external power source; a first monitoring module configured to monitor first power input from the external power source and configured to output a first monitoring result; a second monitoring module configured to monitor second power output from a power module connected to a downstream of the latching relay module and configured to output a second monitoring result; and a control module configured to instruct the latching relay module to turn on based on the first monitoring result and the second monitoring result.

Abstract: According to one embodiment, an information recording apparatus generates a plurality of mutually different title keys so as to conform to rules stipulating the respective ways of handling titles, executes an encryption process on the generated plurality of title keys by using corresponding respective rules and collectively records the encrypted title keys according to the respective rules as a plurality of title key files on a recording medium.

Abstract: According to one embodiment, a storing or recording method of highly confidential data includes sorting a key set (a set of keys and position information items thereof) according to the position information items (for example, position numbers of a column) for each released apparatus, encrypting each pair of the sorted position information items and the respective keys, and storing the encrypted pairs in a non-volatile memory in order of the sorted position information items.

Abstract: Moving image stream data recorded on a recording medium includes title key managing data formed of sets of pointer information items indicating respective encipher data sections, and title keys decoding the respective encipher data sections indicated by the pointer information items. A playback apparatus stores the title key managing data recorded on the recording medium in a storage section. The playback apparatus detects change of the pointer information item included in the moving image stream data read from the recording medium. If the pointer information item has been changed, the playback apparatus obtains a title key corresponding to the pointer information item after change from the storage section, and executes decoding of the input moving image stream data by using the obtained title key.

Abstract: An information device includes a personal information reception processing section which receives personal information read from a recording medium by using a predetermined information reader, and an inquiry request/result reception section which issues, to another information device through a network, a request for an identification inquiry regarding a person indicated by the personal information received by the personal information reception processing section, and receives and outputs an identification inquiry result returned in accordance with the request.

Abstract: A control method for a non-contact communication apparatus communicating information to an external device in a non-contact state is provided. The control method includes the steps of stopping an operation of a control circuit after the control circuit performs a predetermined control operation when processing operations relating to the writing and reading of information is to be executed, and executing a predetermined process by an execution circuit which is scheduled to operate next under control by a logical circuit with the control circuit kept stopped when the supply voltage reaches a predetermined value with the result that a load is applied to the supply power supplied from outside.

Abstract: A control method for a non-contact communication apparatus communicating information to an external device in a non-contact state is provided. The control method includes the steps of stopping an operation of a control circuit after the control circuit performs a predetermined control operation when processing operations relating to the writing and reading of information is to be executed, and executing a predetermined process by an execution circuit which is scheduled to operate next under control by a logical circuit with the control circuit kept stopped when the supply voltage reaches a predetermined value with the result that a load is applied to the supply power supplied from outside.