Patents by Inventor Takeshi Kumaki

Takeshi Kumaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10382708
    Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 13, 2019
    Assignees: BRILLNICS INC., THE RITSUMEIKAN TRUST
    Inventors: Isao Takayanagi, Shunsuke Tanaka, Shinichiro Matsuo, Shunsuke Okura, Shusuke Iwata, Takeshi Fujino, Mitsuru Shiozaki, Takeshi Kumaki, Takaya Kubota, Masayoshi Shirahata
  • Publication number: 20180115723
    Abstract: A solid-state imaging device 10 includes a pixel portion 20 in which a plurality of pixels including photodiodes are arranged in rows and columns, a reading part 90 for reading pixel signals from the pixel portion, and a key generation part 82 which generates a unique key by using at least one of pixel fluctuation information or reading part fluctuation information. According to this configuration, the tamper resistance of the unique key can be secured and consequently alteration and falsification of images can be prevented.
    Type: Application
    Filed: March 18, 2016
    Publication date: April 26, 2018
    Applicants: Brillnics Inc., The Ritsumeikan Trust
    Inventors: Isao Takayanagi, Shunsuke Tanaka, Shinichiro Matsuo, Shunsuke Okura, Shusuke Iwata, Takeshi Fujino, Mitsuru Shiozaki, Takeshi Kumaki, Takaya Kubota, Masayoshi Shirahata
  • Patent number: 7860328
    Abstract: A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 28, 2010
    Assignee: Hiroshima University
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Takeshi Kumaki, Masakatsu Ishizaki
  • Publication number: 20100189351
    Abstract: A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
    Type: Application
    Filed: July 31, 2008
    Publication date: July 29, 2010
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Takeshi Kumaki, Masakatsu Ishizaki
  • Publication number: 20100179976
    Abstract: A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 15, 2010
    Inventors: Masakatsu ISHIZAKI, Takeshi Kumaki, Masaharu Tagami, Yuta Imai, Tetsushi Koide, Hans Jürgen Mattausch, Takayuki Gyoten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto