Abstract: A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

Abstract: A semiconductor device includes: a substrate; and wiring layers on the substrate. Each wiring layer includes: an interlayer insulation film having a wiring groove with a via hole; a copper wiring in the groove and the hole; an barrier metal layer between an inner wall of the groove with the hole and the copper wiring; and an upper barrier metal layer on the interlayer insulation film and covering an upper surface of the copper wiring. The barrier metal layer prevents a copper component in the copper wiring from diffusing into the interlayer insulation film. The copper wiring of an upper layer is electrically coupled with the copper wiring of a lower layer. The upper barrier metal layer of the lower layer prevents a copper component in the copper wiring of the lower layer from diffusing into the interlayer insulation film of the upper layer.

Abstract: A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

Abstract: A semiconductor device includes insulated and separated transistor elements successively connected to one another between ground potential and a predetermined potential. A transistor element at the GND potential side is a first stage and a transistor element at the predetermined potential side is an n-th stage. Resistance elements or capacitance elements are successively connected to one another in series between the GND potential and the predetermined potential. A resistance or capacitance element at the GND potential side is a first stage and a resistance or capacitance element at the predetermined potential side is an n-th stage. Gate terminals of the transistor elements at the respective stages excluding the transistor element at the first stage are successively connected to connection points. An output is taken from the terminal at the predetermined potential side of the transistor element of the n-th stage.

Abstract: A semiconductor device includes insulated and separated transistor elements successively connected to one another between ground potential and a predetermined potential. A transistor element at the GND potential side is a first stage and a transistor element at the predetermined potential side is an n-th stage. Resistance elements or capacitance elements are successively connected to one another in series between the GND potential and the predetermined potential. A resistance or capacitance element at the GND potential side is a first stage and a resistance or capacitance element at the predetermined potential side is an n-th stage. Gate terminals of the transistor elements at the respective stages excluding the transistor element at the first stage are successively connected to connection points. An output is taken from the terminal at the predetermined potential side of the transistor element of the n-th stage.

Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.

Abstract: A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.