Patents by Inventor Takeshi Matsutani

Takeshi Matsutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5498893
    Abstract: A semiconductor device includes a semiconductor layer which has a first surface, and a second surface which is comparatively lower than the first surface. The semiconductor device also has a first material layer formed over the second surface, which includes a first inorganic material which has a hardness exceeding that of the semiconductor layer. The semiconductor device also includes a second material layer which has a hardness less than that of the first material layer, and which is formed in a gap between a sidewall of the first material layer and a sidewall between the first and second surfaces. The first surface of the semiconductor layer is formed by lapping until the first surface of the semiconductor layer is impeded by the first material layer so that the first surface of the semiconductor layer is substantially flush with a top surface of the first material layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 12, 1996
    Assignee: Fujitsu Limited
    Inventors: Shouji Usui, Taketoshi Inagaki, Kiyomasa Kamei, Takeshi Matsutani, Kazunori Imaoka
  • Patent number: 5175119
    Abstract: A polysilicon layer of approximately 500.ANG. in thickness and a PSG layer approximately 3000.ANG. in thickness are sequentially layered on a silicon wafer on which a gate insulating layer is formed; an opening having been formed in the PSG layer. After forming a side wall layer made of PSG of predetermined thickness in the opening, a second polysilicon layer for a leg portion of an inverse-T gate is embedded in the opening and both PSG layers are removed. Then, n.sup.- impurities are doped by ion implantation by using the second polysilicon layer as a mask, forming a LDD region. Another side wall layer is formed on the second polysilicon layer, and then, the first polysilicon layer, exposed outside of the second polysilicon layer and the side wall layer, is etched. Under the side wall layer, that polysilicon layer constituting a top of the inverse-T gate remains. Ion implantation is implemented by using the second polysilicon layer and the side wall layer as masks, such that a n.sup.+ source and n.sup.
    Type: Grant
    Filed: March 18, 1991
    Date of Patent: December 29, 1992
    Assignee: Fujitsu Limited
    Inventor: Takeshi Matsutani
  • Patent number: 5162254
    Abstract: A method for producing a semiconductor device on a semiconductor layer provided on an insulator layer comprises the steps of providing an opening on the semiconductor layer to expose a top surface of the insulator layer, depositing a first material layer that has a hardness exceeding the hardness of the semiconductor layer on the semiconductor layer including the exposed top surface, and patterning the first material layer such that a patterned region of the first inorganic material is left in the opening with a gap separating the patterned region from the side wall of the semiconductor layer.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: November 10, 1992
    Assignee: Fujitsu Limited
    Inventors: Shouji Usui, Taketoshi Inagaki, Kiyomasa Kamei, Takeshi Matsutani, Kazunori Imaoka
  • Patent number: 5143866
    Abstract: A dry etching method for refractory metal or its compound uses a mixed gas of an etchant gas for etching said refractory metal and a deposit gas for depositing said refractory metal. Halide of the etched refractory metal is used as the deposit gas. By using such a mixed gas, the refractory metal is etched at a portion where ion assist is strong, while the refractory metal is deposited at a portion where the ion assist is weak. In the dry etching, the ion mostly hits the surface of the object facing against the anode and hence the ion assist is strong, while the ion assist is weak at the side wall. Accordingly, the refractory metal is etched at the bottom surface of an etched groove, but at the side wall of the groove the refractory metal is deposited. This deposited metal protects the side wall from side etching. Therefore a fine pattern having a high aspect ratio etching is achieved.
    Type: Grant
    Filed: January 17, 1991
    Date of Patent: September 1, 1992
    Assignee: Fujitsu Limited
    Inventor: Takeshi Matsutani
  • Patent number: 4918499
    Abstract: A semiconductor device includes trench capacitors formed in a semiconductor substrate, a trench provided therebetween for isolating the trench capacitors, and a trench capacitor formed in a side wall of the trench for isolating the trench capacitors.
    Type: Grant
    Filed: October 12, 1988
    Date of Patent: April 17, 1990
    Assignee: Fujitsu Limited
    Inventors: Takeshi Matsutani, Kazunori Imaoka