Patents by Inventor Takeshi Matsuyama
Takeshi Matsuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250043415Abstract: A film deposition method includes forming a seed layer containing silicon atoms and nitrogen atoms on a metal film of a substrate by supplying a first silicon-containing gas and a first nitriding gas to the substrate in a state where the substrate is maintained at a first temperature; and forming a bulk layer containing silicon atoms and nitrogen atoms on the seed layer by supplying a second silicon-containing gas and a second nitriding gas to the substrate in a state where the substrate is maintained at a second temperature greater than the first temperature.Type: ApplicationFiled: July 18, 2024Publication date: February 6, 2025Inventors: Yohei MATSUYAMA, Daichi ITO, Takeshi OYAMA
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Patent number: 10279881Abstract: A tiller handle includes: a throttle shaft including first shaft and the second shaft; a conversion mechanism configured to convert rotation of the first shaft into a rectilinear motion of the throttle cable; an engagement pin provided in the second shaft; and a restriction member (shift arm) engaged with the engagement pin depending on a position of a selector in synchronization with the selector to restrict rotation of the second shaft in a throttle valve open direction. The first shaft and the second shaft are configured to relatively rotate each other only by a predetermined angle.Type: GrantFiled: May 3, 2018Date of Patent: May 7, 2019Assignee: SUZUKI MOTOR CORPORATIONInventors: Takeshi Matsuyama, Masatoshi Kimpara, Madoka Suzuki
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Publication number: 20180354596Abstract: A tiller handle includes: a throttle shaft including first shaft and the second shaft; a conversion mechanism configured to convert rotation of the first shaft into a rectilinear motion of the throttle cable; an engagement pin provided in the second shaft; and a restriction member (shift arm) engaged with the engagement pin depending on a position of a selector in synchronization with the selector to restrict rotation of the second shaft in a throttle valve open direction. The first shaft and the second shaft are configured to relatively rotate each other only by a predetermined angle.Type: ApplicationFiled: May 3, 2018Publication date: December 13, 2018Applicant: SUZUKI MOTOR CORPORATIONInventors: Takeshi MATSUYAMA, Masatoshi KIMPARA, Madoka SUZUKI
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Patent number: 4987186Abstract: This invention provides a pressure sensitive adhesive composition comprising an acrylic copolymer component (A) which is at least in part an acetoacetyl group-containing acrylic copolymer and at least one curing component (B) selected from the class consisting of isocyanate compounds, epoxy compounds, aldehyde compounds, non-amino resin amine compounds, metal salts, metal alkoxides, metal chelate compounds, ammonium salts and hydrazine compounds.This adhesive composition is well-balanced in the triad of tack, adhesion, cohesion in adhesion technology and can be advantageously used in various applications such as adhesive tapes and labels.Type: GrantFiled: December 21, 1988Date of Patent: January 22, 1991Assignee: Nippon Gohsei Kagaku Kogyo Kabushiki KaishaInventors: Mamoru Akiyama, Takeshi Matsuyama, Yoshiyuki Yanagida, Akira Yamashita
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Patent number: 4820145Abstract: A polycrystalline silicon wafer having the step of flowing in a predetermined atmosphere molten liquid of silicon base material on a rotating fabrication tray toward a radial direction by means of a centrifugal force produced by the rotation of the tray, thereby forming a thin molten material layer of desired diameter with the molten liquid and solidifying the molten material, comprising a cover, at which a through hole is perforated at the ceiling wall thereof, detachably covered on the tray, a wafer-molding space formed to be surrounded by the cover and the tray, the molten material being filled in the wafer-molding space via the through hole to form a thin molten material layer. Thus, the wafers can be simultaneously formed without production of small projections of the surface of the wafers.Type: GrantFiled: November 3, 1986Date of Patent: April 11, 1989Assignee: Hoxan CorporationInventors: Takashi Yokoyama, Ichiro Hide, Keiji Sawaya, Takeshi Matsuyama
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Patent number: 4656113Abstract: A dye composition prepared by polymerizing an unsaturated monomer in the presence of a quinoneimine dye and an azo initiator in amounts expressed by x.gtoreq.5 and y.gtoreq.0.33x.sup.1.2 wherein x is the amount of the quinoneimine dye in % by weight based on the unsaturated monomer, and y is the amount of the azo initiator in % by weight based on the unsaturated monomer. The composition is useful for preparing toners for developing electrostatic images because of its outstanding charge control effect and also for preparing electrostatic coating powder compositions.Type: GrantFiled: September 19, 1985Date of Patent: April 7, 1987Assignees: Nippon Gosei Kagako Kogyo KK, Orient Chemical Industries, Ltd.Inventors: Tetsuya Ohshima, Hisashi Senshu, Takeshi Matsuyama, Yoji Kawagishi, Takuo Andoh, Takashi Kiryu
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Patent number: 4568624Abstract: A dye composition prepared by polymerizing an unsaturated monomer in the presence of a quinoneimine dye and an azo initiator in amounts expressed by x.gtoreq.5 and y.gtoreq.0.33x.sup.1.2 wherein x is the amount of the quinoneimine dye in % by weight based on the unsaturated monomer, and y is the amount of the azo initiator in % by weight based on the unsaturated monomer. The composition is useful for preparing toners for developing electrostatic images because of its outstanding charge control effect and also for preparing electrostatic coating powder compositions.Type: GrantFiled: September 24, 1984Date of Patent: February 4, 1986Assignees: Nippon Gosei Kagaku Kogyo Kabushiki Kaisha, Orient Chemical Industries Ltd.Inventors: Tetsuya Ohshima, Hisashi Senshu, Takeshi Matsuyama, Yoji Kawagishi, Takuo Andoh, Takashi Kiryu
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Patent number: 4288800Abstract: A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabricating a vertical type junction FET, such double diffusion process is applied to stacked upper and lower semi-conductor layers having opposite conducting types thereby forming a channel region adjacent to the upper semi-conductor layer which functions as a first gate region and forming a second gate region adjacent to the channel region and remote from the first gate region. For fabricating horizontal type junction FET, the double diffusion process stated above is applied to a single semi-conductor layer to form a first gate region thereby forming a channel region adjacent to the first gate region and a second gate region adjacent to the channel region and remote from the first gate region.Type: GrantFiled: August 6, 1979Date of Patent: September 8, 1981Assignee: Nippon Gakki Seizo Kabushiki KaishaInventors: Takashi Yoshida, Takeshi Matsuyama, Tamaki Kuki, Takayuki Kodaka
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Patent number: 4255671Abstract: In an integrated injection logic (IIL) type semiconductor integrated circuit, an injector transistor is formed with a field effect transistor (FET) and an inverter transistor is formed with a bipolar transistor (BPT). The drain region of the FET is merged into the base region of the BPT. The base of the BPT constitutes a logic input and the collector of the BPT constitutes a logic output. The FET may be either of the junction type or of the insulated gate type. The carrier injection efficiency can be improved to approximately unity over a wide range of the injection current.Type: GrantFiled: July 26, 1977Date of Patent: March 10, 1981Assignee: Nippon Gakki Seizo Kabushiki KaishaInventors: Terumoto Nonaka, Takashi Yoshida, Takeshi Matsuyama
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Patent number: 4181542Abstract: A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabricating a vertical type junction FET, such double diffusion process is applied to stacked upper and lower semi-conductor layers having opposite conducting types thereby forming a channel region adjacent to the upper semi-conductor layer which functions as a first gate region and forming a second gate region adjacent to the channel region and remote from the first gate region. For fabricating horizontal type junction FET, the double diffusion process stated above is applied to a single semi-conductor layer to form a first gate region thereby forming a channel region adjacent to the first gate region and a second gate region adjacent to the channel region and remote from the first gate region.Type: GrantFiled: October 25, 1977Date of Patent: January 1, 1980Assignee: Nippon Gakki Seizo Kabushiki KaishaInventors: Takashi Yoshida, Takeshi Matsuyama, Tamaki Kuki, Takayuki Kodaka
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Patent number: 4107725Abstract: A horizontal junction-type field effect transistor having a saturated drain current to drain voltage characteristic and constituting an input transistor and a vertical junction-type field effect transistor having an unsaturated drain current to drain voltage characteristic and constituting an output transistor are connected in cascode fashion to compose a compound field effect transistor.This compound field effect transistor has a saturated characteristic, a high transconductance gm and a high breakdown voltage resembling those of a pentode vacuum tube.This compound field effect transistor is constructed in the form of monolithic integrated circuitry by the combined use of the dielectric isolation technique utilizing mesa groove and the pn-junction isolation technique.Type: GrantFiled: July 30, 1975Date of Patent: August 15, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventors: Takashi Yoshida, Takeshi Matsuyama
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Patent number: 4106044Abstract: A field effect transistor having unsaturated characteristics comprising a plurality of current channels consisting of a semiconductor material of an impurity concentration between 1 .times. 10.sup.13 to 1 .times. 10.sup.15 atoms/c.c., each current channel having a minimum diameter between 2 and 15 .mu.m so that the depletion layer growing from the gate junction nearly but not perfectly closes the current channel at zero gate bias. This junction type field effect transistor provides unsaturated and well aligned parallel characteristic curves and reduces power loss as compared to conventional unsaturated type vertical field effect transistors.Type: GrantFiled: May 27, 1977Date of Patent: August 8, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventors: Takashi Yoshida, Masao Kosugi, Takeshi Matsuyama