Patents by Inventor Takeshi Miyaba
Takeshi Miyaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11728642Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.Type: GrantFiled: September 14, 2021Date of Patent: August 15, 2023Assignee: Kioxia CorporationInventors: Shigefumi Ishiguro, Yasuhiro Suematsu, Takeshi Miyaba, Kimimasa Imai, Maya Inagaki
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Publication number: 20220285934Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.Type: ApplicationFiled: September 14, 2021Publication date: September 8, 2022Applicant: Kioxia CorporationInventors: Shigefumi ISHIGURO, Yasuhiro SUEMATSU, Takeshi MIYABA, Kimimasa IMAI, Maya INAGAKI
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Patent number: 8213882Abstract: A common resistor is connected to load impedances that convert differential currents respectively generated by current sources into differential voltages. A constant current generated by the current sources is supplied to the common resistor to cause the common resistor to generate an in-phase current and set a common potential.Type: GrantFiled: March 16, 2010Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Ueno, Takeshi Ueno, Takeshi Miyaba
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Publication number: 20100296600Abstract: A common resistor is connected to load impedances that convert differential currents respectively generated by current sources into differential voltages. A constant current generated by the. current sources is supplied to the common resistor to cause the common resistor to generate an in-phase current and set a common potential.Type: ApplicationFiled: March 16, 2010Publication date: November 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi Ueno, Takeshi Ueno, Takeshi Miyaba
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Patent number: 7808280Abstract: A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along the signal line, each of which operates with a substrate bias potential, and multiple contact cells disposed in the wiring region in parallel with the wiring direction of the signal line, each being associated with each of the multiple standard cells and providing the substrate bias potential to the associated standard cell.Type: GrantFiled: May 27, 2009Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Miyaba
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Publication number: 20090230995Abstract: A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along the signal line, each of which operates with a substrate bias potential, and multiple contact cells disposed in the wiring region in parallel with the wiring direction of the signal line, each being associated with each of the multiple standard cells and providing the substrate bias potential to the associated standard cell.Type: ApplicationFiled: May 27, 2009Publication date: September 17, 2009Applicant: Kabushiki Kaisha ToshibaInventor: Takeshi MIYABA
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Patent number: 7203120Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: GrantFiled: November 9, 2005Date of Patent: April 10, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Patent number: 7180796Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: GrantFiled: November 9, 2005Date of Patent: February 20, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20060055453Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: ApplicationFiled: November 9, 2005Publication date: March 16, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20060055452Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: ApplicationFiled: November 9, 2005Publication date: March 16, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Patent number: 6996024Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: GrantFiled: June 14, 2004Date of Patent: February 7, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20040240271Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: ApplicationFiled: June 14, 2004Publication date: December 2, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Patent number: 6813130Abstract: A first power wire supplies a power potential to a circuit having a first function. A first ground wire supplies a ground potential to the circuit having the first function. A first protection circuit is connected between the first power wire and first ground wire, and protects the circuit having the first function. A second power wire supplies a power potential to a circuit having a second function. A second ground wire supplies a ground potential to the circuit having the second function. A second protection circuit is connected between the second power wire and the second ground wire, and protects the circuit having the second function. The element is disposed in at least one of intervals between the first power wire and the second power wire and between the first ground wire and the second ground wire, and brings one of the intervals into a disconnected state.Type: GrantFiled: June 6, 2002Date of Patent: November 2, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Miyaba
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Patent number: 6771547Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: GrantFiled: June 19, 2003Date of Patent: August 3, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20030210089Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: ApplicationFiled: June 19, 2003Publication date: November 13, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20030202309Abstract: A first power wire supplies a power potential to a circuit having a first function. A first ground wire supplies a ground potential to the circuit having the first function. A first protection circuit is connected between the first power wire and first ground wire, and protects the circuit having the first function. A second power wire supplies a power potential to a circuit having a second function. A second ground wire supplies a ground potential to the circuit having the second function. A second protection circuit is connected between the second power wire and the second ground wire, and protects the circuit having the second function. The element is disposed in at least one of intervals between the first power wire and the second power wire and between the first ground wire and the second ground wire, and brings one of the intervals into a disconnected state.Type: ApplicationFiled: June 6, 2002Publication date: October 30, 2003Inventor: Takeshi Miyaba
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Patent number: 6605986Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: GrantFiled: October 8, 2002Date of Patent: August 12, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20030112056Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: ApplicationFiled: October 8, 2002Publication date: June 19, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Patent number: 6487120Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: GrantFiled: May 25, 2001Date of Patent: November 26, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi
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Publication number: 20020003724Abstract: There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.Type: ApplicationFiled: May 25, 2001Publication date: January 10, 2002Inventors: Toru Tanzawa, Takeshi Miyaba, Shigeru Atsumi