Abstract: It is to provide a process for manufacturing potable water from a liquid to be treated, such as seawater by using forward osmosis membrane, wherein the solution after the separation of water from dilute draw solution diluted by the migration of water from the liquid to be treated, is stably regenerated and reutilized and an apparatus therefor, and the process and apparatus are a process for manufacturing potable water which comprises, a forward osmosis step wherein a liquid of which solvent is water is allowed to contact with a draw solution produced by dissolving a prescribed amount of a volatile material in water through a semi-permeable membrane, and water in said liquid is allowed to migrate to said draw solution through said semi-permeable membrane, a distillation step wherein a dilute draw solution having been diluted with water which was produced in said step is adjusted to a prescribed temperature, and then is delivered to a distillation column where gas comprising the volatile material and water vapo

Abstract: A self-refreshing system incorporated in a semiconductor dynamic random access memory device is responsive to an external data signal indicative of a time interval of a refresh cycle so as to repeat a refreshing operation on memory cells at the time intervals, and the current consumption in the refresh mode is decreased through the optimization of the refresh cycle.

Abstract: A semiconductor memory comprises memory cell arrays and data amplifiers, four or more respectively, and two common read buses for them. Each data amplifier outputs the first and second data having respective levels complementary to each other. It further comprises the first and second logic circuits. Each logic circuit is composed of a plurality of transistors, each being located adjacent to the respective corresponding data amplifier, to the gate of each the first and second data being applied, and the drain of each being connected to the two read buses. The semiconductor memory further comprises the third logic circuit into which the data from the two read buses are input. The number of data buses needed can be reduced to only three in total for write and read operations independent of the number of memory cell arrays, contributing to minimization of chip area.

Abstract: A serial access memory device with the improved cascade buffer circuit for controlling serial access operation which has a small number of external terminals is disclosed. The cascade buffer circuit includes first and second external terminals, a first control circuit for enabling the memory device to perform write operation and read operation when the level at the first external terminal rises or falls and when the level at the first external terminal falls or rises, respectively and a second control circuit for operatively causing the second external terminal to rise or fall when the memory device completes write operation and causing the second external terminal to fall or rise when the memory device completes read operation, respectively.

Abstract: A semiconductor memory system with a fully automated built-in refresh control circuitry, comprising a dynamic random access memory cell array, a data transfer gate circuit through which data signals are to be transferred to or from the memory cell array, a data transfer request signal generator to produce a signal requesting activation of the gate circuit, a refresh request signal generator to produce a signal to request refreshing of the memory cell array, a refresh address counter for storing an address signal representing a memory address where the memory cell array is to be refreshed, and a refresh test control circuit responsive to the signals produced by the data transfer request and refresh request signal generators and operative to produce from the signal from the data transfer request signal generator a control signal to check the refresh address counter for proper operation during a refresh test cycle which is initiated by a signal supplied from an external source.