Abstract: An input/output channel apparatus includes a channel processing section and plural channel units transfers data between a main memory and peripheral devices in an electronic computer system. The data transfer speed is directly controlled by the data transfer speed changing mechanism in each channel unit in accordance with the operating condition of the data buffer. Further, the priority of the data chaining process is changed in accordance with the amount of data stored in the data buffer.

Abstract: An interface system for use with an electronic computer including a CPU, a main memory, an input/output channel unit to which a group of latches is connected by a ring transmitting path and adapted to serve as a serial register, and a service processing unit including an operator's console control unit for performing a resetting operation or the like for each of such units, wherein the service processing unit affords read/write operations of data transmitted from the serial register by itself, and which is characterized by an additional console shift register provided in the input/output channel unit, which allows an interface to be implemented between the input/output channel unit and the operator's console control unit by the reading/writing of data into and from the console shift register.