Patents by Inventor Takeshi Noma
Takeshi Noma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12047115Abstract: First transmission device includes a first counter that generates counter value incremented in a specified cycle. Second transmission device includes a second counter that generates counter value incremented in the specified cycle. Polarization variation monitoring device acquires a first counter value generated by the first counter and a second counter value extracted by the first transmission device from a received frame transmitted from the second transmission device when the first transmission device detects polarization variation, and a third counter value generated by the second counter and a fourth counter value extracted by the second transmission device from a frame transmitted from the first transmission device when the second detector detects the polarization variation. The polarization variation monitoring device determines an occurrence position of the polarization variation based on the first counter value, the second counter value, the third counter value and the fourth counter value.Type: GrantFiled: September 9, 2022Date of Patent: July 23, 2024Assignee: FUJITSU LIMITEDInventors: Ichiro Yokokura, Junichi Sugiyama, Makoto Shimizu, Toshihiro Suzuki, Takeshi Noma, Hisao Nakashima, Yuji Ikegami
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Publication number: 20230087839Abstract: First transmission device includes a first counter that generates counter value incremented in a specified cycle. Second transmission device includes a second counter that generates counter value incremented in the specified cycle. Polarization variation monitoring device acquires a first counter value generated by the first counter and a second counter value extracted by the first transmission device from a received frame transmitted from the second transmission device when the first transmission device detects polarization variation, and a third counter value generated by the second counter and a fourth counter value extracted by the second transmission device from a frame transmitted from the first transmission device when the second detector detects the polarization variation. The polarization variation monitoring device determines an occurrence position of the polarization variation based on the first counter value, the second counter value, the third counter value and the fourth counter value.Type: ApplicationFiled: September 9, 2022Publication date: March 23, 2023Applicant: FUJITSU LIMITEDInventors: Ichiro YOKOKURA, Junichi SUGIYAMA, Makoto SHIMIZU, Toshihiro SUZUKI, Takeshi NOMA, Hisao NAKASHIMA, Yuji IKEGAMI
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Publication number: 20230082206Abstract: First transmission device includes a first counter that generates counter value incremented in a specified cycle. Second transmission device includes a second counter that. generates counter value incremented in the specified cycle. Polarization variation monitoring device acquires a first counter value generated by the first counter and a second counter value extracted by the first transmission device from a received frame transmitted from the second transmission device when the first transmission device detects polarization variation, and a third counter value generated by the second counter and a fourth counter value extracted by the second transmission device from a frame transmitted from the first transmission. device when the second detector detects the polarization variation. The polarization variation monitoring device determines an occurrence position of the polarization variation based on the first counter value, the second counter value, the third counter value and the fourth counter value.Type: ApplicationFiled: June 16, 2022Publication date: March 16, 2023Applicant: FUJITSU LIMITEDInventors: Ichiro YOKOKURA, Junichi SUGIYAMA, Makoto SHIMIZU, Toshihiro SUZUKI, Takeshi NOMA, Hisao NAKASHIMA
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Publication number: 20210103307Abstract: A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Inventors: Kohei TANAKA, Hidefumi YOSHIDA, Takeshi NOMA, Ryo YONEBAYASHI, Takayuki NISHIYAMA, Mitsuhiro MURATA, Yosuke IWATA
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Patent number: 10901442Abstract: A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.Type: GrantFiled: June 18, 2019Date of Patent: January 26, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Kohei Tanaka, Hidefumi Yoshida, Takeshi Noma, Ryo Yonebayashi, Takayuki Nishiyama, Mitsuhiro Murata, Yosuke Iwata
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Patent number: 10809581Abstract: Provided is an active matrix substrate 20a in which either a plurality of source lines (data lines) 15S or a plurality of gate lines 13G, as constituent elements of the active matrix substrate 20a, are vertical lines extending in the longitudinal direction, and the other are horizontal lines. Among a plurality of pixel control elements 16T that are provided in correspondence to a plurality of pixels and are connected with the data line 15S and the gate lines 13G so as to control display of the corresponding pixels, respectively, a part of the pixel control elements 16T connected with one same horizontal line are arranged on one side with respect to the respective vertical lines to which the pixel control elements are connected, the side being different from a side on which the other pixel control elements connected with the same horizontal line are arranged.Type: GrantFiled: November 20, 2015Date of Patent: October 20, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Takayuki Nishiyama, Kohhei Tanaka, Takeshi Noma, Ryo Yonebayashi, Yosuke Iwata
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Patent number: 10634968Abstract: Provided is an active matrix substrate that includes gate lines (13G), source lines, pixel switching elements, a plurality of gate line driving circuits (11) that control potentials of the gate lines, in the display region, and control signal lines (15L1) that supply a control signal to the gate line driving circuits (11). Each of the gate line driving circuits (11) includes driving switching elements and a capacitor. At least part of the driving switching elements and the capacitor are arranged at positions closer to, not the gate line (13G) corresponding to the gate line driving circuit (11), but another gate line (13G).Type: GrantFiled: December 18, 2018Date of Patent: April 28, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Takeshi Noma, Kohhei Tanaka, Takayuki Nishiyama, Ryo Yonebayashi
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Patent number: 10627688Abstract: An active matrix substrate is provided that includes: a plurality of source lines (data lines) 15S; a plurality of lines that intersect with the source lines 15S, and include at least a plurality of gate lines 13G; a gate driver (driving circuit) 11 that includes a plurality of switching elements 18, and are connected to at least a part of the lines, so as to control potentials of the lines according to a control signal; and a plurality of pixel control elements 16T that are provided in correspondence to a plurality of pixels that compose a display region, and are connected with the data lines 15S and the gate lines 13G, so as to control display of the corresponding pixels, respectively. Either the data lines 15S or the gate lines 13G are vertical lines while the others are horizontal lines, and intervals of the horizontal lines are irregular intervals.Type: GrantFiled: November 20, 2015Date of Patent: April 21, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Takayuki Nishiyama, Kohhei Tanaka, Takeshi Noma, Yosuke Iwata, Ryo Yonebayashi
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Publication number: 20190302815Abstract: A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Inventors: Kohei TANAKA, Hidefumi YOSHIDA, Takeshi NOMA, Ryo YONEBAYASHI, Takayuki NISHIYAMA, Mitsuhiro MURATA, Yosuke IWATA
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Patent number: 10410594Abstract: The present invention provides a technique for reducing pixel brightness unevenness in a case where driving circuits for switching gate lines to a selected or non-selected state are provided in pixels. An active matrix substrate includes, in each pixel PIX, a pixel-switching element 10 and a pixel electrode PXB. Further, in the active matrix substrate, a plurality of driving circuits that switch one gate line to a selected or non-selected state are arranged in the pixels, and control lines 16 that supply control signals to the driving circuits are arranged in the pixels. Each driving circuit includes a plurality of switching elements and an internal line netA.Type: GrantFiled: November 19, 2015Date of Patent: September 10, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Ryo Yonebayashi, Kohhei Tanaka, Takeshi Noma, Takayuki Nishiyama
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Patent number: 10365674Abstract: A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.Type: GrantFiled: September 21, 2017Date of Patent: July 30, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Kohei Tanaka, Hidefumi Yoshida, Takeshi Noma, Ryo Yonebayashi, Takayuki Nishiyama, Mitsuhiro Murata, Yosuke Iwata
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Publication number: 20190121213Abstract: Provided is an active matrix substrate that includes gate lines (13G), source lines, pixel switching elements, a plurality of gate line driving circuits (11) that control potentials of the gate lines, in the display region, and control signal lines (15L1) that supply a control signal to the gate line driving circuits (11). Each of the gate line driving circuits (11) includes driving switching elements and a capacitor. At least part of the driving switching elements and the capacitor are arranged at positions closer to, not the gate line (13G) corresponding to the gate line driving circuit (11), but another gate line (13G).Type: ApplicationFiled: December 18, 2018Publication date: April 25, 2019Inventors: TAKESHI NOMA, KOHHEI TANAKA, TAKAYUKI NISHIYAMA, RYO YONEBAYASHI
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Patent number: 10235956Abstract: A technique of, in the case of changing, at predetermined time intervals, a drive circuit for switching a gate line to a selected state, preventing a stopped drive circuit from malfunctioning is provided. Each of a plurality of drive circuits provided for each gate line in an active-matrix substrate includes: a selection circuit unit including an output switching element that is turned on to apply a voltage to the gate line in response to a control signal; an internal line connected to a gate terminal of the output switching element and the gate line; and a potential control circuit unit connected to the internal line for controlling a potential of the internal line in response to the control signal.Type: GrantFiled: April 21, 2015Date of Patent: March 19, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Kohhei Tanaka, Takayuki Nishiyama, Takeshi Noma, Ryo Yonebayashi
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Patent number: 10216042Abstract: The present invention provides a liquid-crystal display device capable of maintaining a high voltage holding ratio even without an alignment film. The liquid-crystal display device of the present invention includes a pair of substrates, a liquid crystal layer which is sandwiched between the substrates and which contains a liquid crystal material, and a polymer layer which is disposed on a surface of each of the substrates and which controls the alignment of liquid crystal molecules. The outermost surfaces of both the substrates comprise substantially no alignment film. The polymer layer is formed by polymerizing one or more radical polymerizable monomer species added to the liquid crystal layer. At least one species of the one or more radical polymerizable monomer species is a biphenyl compound having a specific structure.Type: GrantFiled: January 18, 2017Date of Patent: February 26, 2019Assignee: MERCK PATENT GMBHInventors: Takeshi Noma, Youhei Nakanishi, Masanobu Mizusaki
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Patent number: 10191344Abstract: Provided is an active matrix substrate that includes gate lines (13G), source lines, pixel switching elements, a plurality of gate line driving circuits (11) that control potentials of the gate lines, in the display region, and control signal lines (15L1) that supply a control signal to the gate line driving circuits (11). Each of the gate line driving circuits (11) includes driving switching elements and a capacitor. At least part of the driving switching elements and the capacitor are arranged at positions closer to, not the gate line (13G) corresponding to the gate line driving circuit (11), but another gate line (13G).Type: GrantFiled: November 19, 2015Date of Patent: January 29, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Takeshi Noma, Kohhei Tanaka, Takayuki Nishiyama, Ryo Yonebayashi
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Patent number: 10121440Abstract: Provided is a display device causing less noise on a signal. A display device (10) includes a plurality of signal lines (SL), a plurality of gate lines (GL), and a driving unit. The plurality of gate lines crosses the plurality of signal lines. The driving unit is connected to the plurality of gate lines and controls a potential of each of the gate lines. The driving unit includes a plurality of gate drivers (11) and a plurality of lines. The gate drivers are disposed in a display region, and at least one of the gate drivers is connected to each of the gate lines. The lines are each provided with a potential for operation of one of the gate drivers. Each of the lines crosses one of the signal lines. The plurality of lines includes a first line (17A) and a second line (17B). The driving unit switches a potential of the first line at predetermined timing.Type: GrantFiled: April 27, 2015Date of Patent: November 6, 2018Assignee: Sharp Kabushiki KaishaInventors: Takayuki Nishiyama, Kohhei Tanaka, Takeshi Noma, Ryo Yonebayashi
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Patent number: 10115369Abstract: To reduce the parasitic capacitance of a driving circuit and definitely switches a gate line to a selection state, an active matrix substrate is provided. The active matrix substrate includes a driving circuit that switches a gate line (13G) to a selection state in a pixel region defined by a source line (15S) and the gate line (13G). The driving circuit includes: a plurality of switching elements including an output switching element (TFT-F) that supplies a selection voltage to the gate line; and an internal line (netA) to which a gate terminal of the output switching element (TFT-F) and at least a first switching element of the switching elements other than the output switching element are connected. The active matrix substrate includes a reduction part (C1 and C2) that reduce the parasitic capacitance of the driving circuit in the pixel region in which at least one of the internal line and the first switching element is located.Type: GrantFiled: April 22, 2015Date of Patent: October 30, 2018Assignee: SHARP KABUSHIKI KAISHAInventors: Takeshi Noma, Kohhei Tanaka, Takayuki Nishiyama, Ryo Yonebayashi
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Patent number: 10078239Abstract: Provided is a sensor-equipped display device (1) that includes: a first substrate (20a); a second substrate (20b) opposed to the first substrate (20a); a liquid crystal layer (LC); a plurality of first lines (15) extending in a first direction in a pixel area (AA); second lines extending in a second direction that is different from the first direction; pixel switching elements that are provided for pixels, respectively, and are connected to the first lines and the second lines; a plurality of sensor electrodes (SE, DL) provided at positions that overlap the pixel area on at least one of the first substrate and the second substrate, for detecting the contact or approach of the object; and a plurality of sensor lead-out lines that are provided in parallel to the first lines or the second lines in the pixel area on the first substrate, and are connected to the sensor electrodes, respectively.Type: GrantFiled: April 27, 2015Date of Patent: September 18, 2018Assignee: SHARP KABUSHIKI KAISHAInventors: Yasuhiro Sugita, Kohhei Tanaka, Takeshi Noma, Takayuki Nishiyama, Ryo Yonebayashi, Kenshi Tada, Shinji Yamagishi, Jean Mugiraneza
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Patent number: 10059881Abstract: An aspect of the present invention provides a monomer from which a polymer layer capable of keeping high display quality even in high temperature and high humidity environments can be formed. The monomer in an aspect of the present invention is a compound represented by P-Sp1-Z2-A1-(Z1-A2)n1-Z3-Sp2-P: in the formula, P denotes the same or different radical polymerizable group; and at least one of Z1, Z2, and Z3 denotes —NRCO— or —CONR— group.Type: GrantFiled: October 17, 2013Date of Patent: August 28, 2018Assignees: SHARP KABUSHIKI KAISHA, TOYO GOSEI CO., LTD.Inventors: Masanobu Mizusaki, Youhei Nakanishi, Takeshi Noma, Satoshi Enomoto
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Patent number: 9983441Abstract: A liquid crystal display device includes: a polymer layer that controls the alignment of liquid crystal molecules on at least one of the first substrate and the second substrate. The polymer layer is formed by polymerizing one or more radical-polymerizable monomers added to the liquid crystal layer. At least one of the radical-polymerizable monomers is a compound represented by P-Sp1-Z2-A1-(Z1-A2)n1-Z3-Sp2-P. In an example encompassed by the formula, P represents a radical-polymerizable group. Sp1 and Sp2 each represent a direct bond or an alkylene group. A1 represents a divalent aromatic hydrocarbon group. A2 represents a phenylene group. Z1, Z2, and Z3 may be the same or different. At least one of Z1, Z2, and Z3 represents a direct bond, or an —NRCO— group or —CONR— group. R represents a hydrogen atom or a C1-C6 linear alkyl group or alkenyl group. n1 is 0 or 1.Type: GrantFiled: October 17, 2013Date of Patent: May 29, 2018Assignee: MERCK PATENT GMBHInventors: Youhei Nakanishi, Masanobu Mizusaki, Takeshi Noma