Patents by Inventor Takeshi Ohgami
Takeshi Ohgami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10354705Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a plurality of sense amplifier control circuits coupled to a plurality of corresponding sense amplifiers, wherein each sense amplifier control circuit of the plurality of sense amplifier control circuits provides one or more control signals to a corresponding sense amplifier of a plurality of sense amplifiers; and a driver that provides a selection signal to a plurality of word drivers responsive, at least in part, to a first control signal that is responsive to the one or more control signals from the plurality of sense amplifier control circuits.Type: GrantFiled: July 5, 2017Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventor: Takeshi Ohgami
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Publication number: 20190013055Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a plurality of sense amplifier control circuits coupled to a plurality of corresponding sense amplifiers, wherein each sense amplifier control circuit of the plurality of sense amplifier control circuits provides one or more control signals to a corresponding sense amplifier of a plurality of sense amplifiers; and a driver that provides a selection signal to a plurality of word drivers responsive, at least in part, to a first control signal that is responsive to the one or more control signals from the plurality of sense amplifier control circuits.Type: ApplicationFiled: July 5, 2017Publication date: January 10, 2019Applicant: Micron Technology, Inc.Inventor: Takeshi Ohgami
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Patent number: 9418711Abstract: A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an FX driver for selecting a word driver selecting line based on bits regardless of the bits of the row address, and a plurality of sub-word drivers selected by the main word line and the word driver selecting line to drive the corresponding sub-word line are arranged.Type: GrantFiled: October 8, 2014Date of Patent: August 16, 2016Assignee: Micron Technology, Inc.Inventor: Takeshi Ohgami
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Patent number: 9019787Abstract: A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.Type: GrantFiled: May 7, 2013Date of Patent: April 28, 2015Assignee: PS4 Luxco S.A.R.L.Inventors: Yasuhiro Matsumoto, Noriaki Mochida, Takeshi Ohgami, Daiki Izawa
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Publication number: 20150098260Abstract: A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an FX driver for selecting a word driver selecting line based on bits regardless of the bits of the row address, and a plurality of sub-word drivers selected by the main word line and the word driver selecting line to drive the corresponding sub-word line are arranged.Type: ApplicationFiled: October 8, 2014Publication date: April 9, 2015Inventor: TAKESHI OHGAMI
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Patent number: 8797778Abstract: A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats.Type: GrantFiled: December 23, 2009Date of Patent: August 5, 2014Assignee: PS4 Luxco S.a.r.l.Inventor: Takeshi Ohgami
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Publication number: 20130308403Abstract: Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation.Type: ApplicationFiled: May 15, 2013Publication date: November 21, 2013Applicant: Elpida Memory, Inc.Inventors: Izumi NAKAI, Takeshi OHGAMI, Noriaki MOCHIDA, Yasuhiro MATSUMOTO
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Publication number: 20130301330Abstract: A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.Type: ApplicationFiled: May 7, 2013Publication date: November 14, 2013Applicant: Elpida Memory, Inc.Inventors: Yasuhiro MATSUMOTO, Noriaki MOCHIDA, Takeshi OHGAMI, Daiki IZAWA
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Patent number: 8508982Abstract: A semiconductor device includes a first memory cell, a first line, a second line and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.Type: GrantFiled: May 16, 2011Date of Patent: August 13, 2013Assignee: Elpida Memory, Inc.Inventor: Takeshi Ohgami
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Patent number: 8477536Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: GrantFiled: August 9, 2012Date of Patent: July 2, 2013Assignee: Elpida Memory, Inc.Inventor: Takeshi Ohgami
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Publication number: 20120309156Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Takeshi OHGAMI
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Patent number: 8259496Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: GrantFiled: January 26, 2012Date of Patent: September 4, 2012Assignee: Elpida Memory, Inc.Inventor: Takeshi Ohgami
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Publication number: 20120120706Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: ApplicationFiled: January 26, 2012Publication date: May 17, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Takeshi OHGAMI
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Patent number: 8130546Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: GrantFiled: January 29, 2010Date of Patent: March 6, 2012Assignee: Elpida Memory, IncInventor: Takeshi Ohgami
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Patent number: 8105907Abstract: To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.Type: GrantFiled: January 29, 2010Date of Patent: January 31, 2012Assignee: Elpida Memory, Inc.Inventors: Eiji Hasunuma, Shigeru Shiratake, Takeshi Ohgami
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Publication number: 20110292717Abstract: A semiconductor device may include, but is not limited to: a first memory cell; a first line; a second line; and a first capacitor. The first line is coupled to the first memory cell. The first line supplies a first voltage to the first memory cell. The second line is supplied with a fixed voltage. The first capacitor is coupled between the first and second lines.Type: ApplicationFiled: May 16, 2011Publication date: December 1, 2011Applicant: Elpida Memory, Inc.Inventor: Takeshi Ohgami
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Patent number: 7903489Abstract: A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.Type: GrantFiled: June 15, 2007Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Takeshi Ohgami, Seiji Narui
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Publication number: 20100195431Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: ApplicationFiled: January 29, 2010Publication date: August 5, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Takeshi OHGAMI
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Publication number: 20100197097Abstract: To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.Type: ApplicationFiled: January 29, 2010Publication date: August 5, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Eiji HASUNUMA, Shigeru SHIRATAKE, Takeshi OHGAMI
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Patent number: RE47227Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.Type: GrantFiled: July 2, 2015Date of Patent: February 5, 2019Assignee: LONGITUDE LICENSING LIMITEDInventor: Takeshi Ohgami