Patents by Inventor Takeshi Oikawa

Takeshi Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11215106
    Abstract: A cooling device includes a surrounding member, an air inlet, an air outlet, and a flow-path-formation mechanism. The surrounding member is configured to surround an engine. The air inlet is formed in the surrounding member. The air outlet is formed in the surrounding member and is to be coupled to an intake pipe of the engine. The flow-path-formation mechanism is configured to form a flow path that allows outside air to circulate to the air outlet from the air inlet when a temperature of the engine or a temperature inside the surrounding member is greater than or equal to a predetermined temperature.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 4, 2022
    Assignee: SUBARU CORPORATION
    Inventor: Takeshi Oikawa
  • Publication number: 20210062706
    Abstract: A cooling device includes a surrounding member, an air inlet, an air outlet, and a flow-path-formation mechanism. The surrounding member is configured to surround an engine. The air inlet is formed in the surrounding member. The air outlet is formed in the surrounding member and is to be coupled to an intake pipe of the engine. The flow-path-formation mechanism is configured to form a flow path that allows outside air to circulate to the air outlet from the air inlet when a temperature of the engine or a temperature inside the surrounding member is greater than or equal to a predetermined temperature.
    Type: Application
    Filed: July 27, 2020
    Publication date: March 4, 2021
    Applicant: SUBARU CORPORATION
    Inventor: Takeshi OIKAWA
  • Patent number: 8588038
    Abstract: An optical pickup has a laser light source, beam splitter, collimator lens, reflection mirror, objective lens and photo detector are mounted in a case. An objective lens actuator includes a magnetic member and magnet. The optical pickup may become contaminated by uncured adhesive remaining at the edges of the adhesive surfaces of the magnet and the magnetic member that is transferred to the optical pickup via finger cots or tweezers, etc. In an adhesion step between the magnet and the magnetic member, in which part of a groove near to the center of the surface has a small depth and part of the groove near to the outer circumference of the surface has a large depth, an adhesive is drawn toward the center of the surface of the magnetic member by a capillary phenomenon and is prevented from spreading along the outer edge of the surface.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 19, 2013
    Assignee: Hitachi Media Electronics Co., Ltd.
    Inventors: Yasushi Kinoshita, Souichirou Yamada, Takeshi Oikawa
  • Publication number: 20130083635
    Abstract: An optical pickup has a laser light source, beam splitter, collimator lens, reflection mirror, objective lens and photo detector are mounted in a case. An objective lens actuator includes a magnetic member and magnet. The optical pickup may become contaminated by uncured adhesive remaining at the edges of the adhesive surfaces of the magnet and the magnetic member that is transferred to the optical pickup via finger cots or tweezers, etc. In an adhesion step between the magnet and the magnetic member, in which part of a groove near to the center of the surface has a small depth and part of the groove near to the outer circumference of the surface has a large depth, an adhesive is drawn toward the center of the surface of the magnetic member by a capillary phenomenon and is prevented from spreading along the outer edge of the surface.
    Type: Application
    Filed: March 23, 2012
    Publication date: April 4, 2013
    Applicant: HITACHI MEDIA ELECTRONICS CO., LTD.
    Inventors: Yasushi KINOSHITA, Souichirou YAMADA, Takeshi OIKAWA
  • Publication number: 20130045318
    Abstract: To provide a salty taste enhancer which exerts a flavor enhancing effect comparable to sodium chloride without imparting any undesirable flavor such as harsh taste or odd smell, a method for producing the same, a kelp extract comprising the salty taste enhancer, and a food or drink having enhanced salty taste and flavor which comprises the salty taste enhancer or the kelp extract. A salty taste enhancer which comprises a volatile component with a molecular weight of less than 200 derived from a kelp.
    Type: Application
    Filed: April 8, 2011
    Publication date: February 21, 2013
    Applicant: TAKASAGO INTERNATIONAL CORPORATION
    Inventors: Akihiko Watanabe, Azusa Nakatoh, Takeshi Oikawa
  • Patent number: 8116163
    Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Oikawa
  • Publication number: 20110063015
    Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Inventor: Takeshi OIKAWA
  • Patent number: 7859923
    Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Oikawa
  • Publication number: 20090245006
    Abstract: The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventor: Takeshi Oikawa
  • Patent number: 6548884
    Abstract: A semiconductor device having a fuse evaluation circuit is provided. Fuse evaluation circuit (100) can include, a reference voltage generation circuit (110), a fuse circuit (120-n), and a fuse evaluation control circuit (130). Fuse circuit (120-n) can include a fuse (Fn) and evaluation transistor (Tn) arranged in-series and providing an evaluation node (Nn) at their connection. Reference voltage generation circuit (110) can provide a reference voltage (VG1) at a control gate of evaluation transistor (Tn). Fuse evaluation control circuit (130) can vary the impedance of the evaluation transistor (Tn) by varying the potential of reference voltage (VG1). Fuse evaluation circuit (100) can evaluate the condition of fuse (Fn) accordingly.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: April 15, 2003
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventor: Takeshi Oikawa
  • Publication number: 20010052633
    Abstract: A semiconductor device having a fuse evaluation circuit is provided. Fuse evaluation circuit (100) can include, a reference voltage generation circuit (110), a fuse circuit (120-n), and a fuse evaluation control circuit (130). Fuse circuit (120-n) can include a fuse (Fn) and evaluation transistor (Tn) arranged in series and providing an evaluation node (Nn) at their connection. Reference voltage generation circuit (110) can provide a reference voltage (VG1) at a control gate of evaluation transistor (Tn). Fuse evaluation control circuit (130) can vary the impedance of the evaluation transistor (Tn) by varying the potential of reference voltage (VG1). Fuse evaluation circuit (100) can evaluate the condition of fuse (Fn) accordingly.
    Type: Application
    Filed: May 7, 2001
    Publication date: December 20, 2001
    Inventor: Takeshi Oikawa
  • Patent number: 5264737
    Abstract: An OS signal generation circuitry comprises a plurality of OS signal generating circuits receiving corresponding address bits of an address so as to generate individual OS signals, respectively, which are supplied to an OR circuit for generating an original OS signal. This original OS signal is supplied to a rising detection circuit, which outputs a second OS signal generated on the basis of the detected rising of the original OS signal and having a substantially constant width. Another OR circuit receives the original OS signal and the second OS signal and generates an output OS signal having the constant OS width. Accordingly, the OS signal can have the OS width which does not vary dependently upon the number of address bits actually changing their logical level.
    Type: Grant
    Filed: August 6, 1992
    Date of Patent: November 23, 1993
    Assignee: NEC Corporation
    Inventor: Takeshi Oikawa
  • Patent number: 4832621
    Abstract: A probe for an in-circuit emulator comprising a flexible substrate composed of a base film, a pattern provided on a central portion of the base film, plastic parts mounted on both ends of the base film, a connecting element detachably provided at one end of the flexible substrate, and reinforcing members mounted on the plastic parts.
    Type: Grant
    Filed: January 30, 1987
    Date of Patent: May 23, 1989
    Assignee: Ando Electric Co., Ltd.
    Inventors: Hironobu Asai, Takeshi Oikawa
  • Patent number: 4749356
    Abstract: A probe for an in-circuit emulator comprises flexible substrates, pins provided at one end of the substrates for connecting the flexible substrates with an LSI package, a base mounted on the flexible substrates and having a penetration hole for holding the pins, and a presser plate mounted on the flexible substrates and having a hole, characterized in that the base and presser plate sandwich the flexible substrates and pins for connecting the flexible substrates with the pins.
    Type: Grant
    Filed: January 30, 1987
    Date of Patent: June 7, 1988
    Assignee: Ando Electric Co., Ltd.
    Inventors: Hironobu Asai, Takeshi Oikawa