Patents by Inventor Takeshi Oomori

Takeshi Oomori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220002617
    Abstract: The present invention addresses the problem of providing a scintillator which has excellent impact resistance and favorable workability and moldability. The problem is solved by a resin-phosphor composite scintillator which contains a resin and a phosphor and is capable of converting irradiated radiation into visible light. In this composite scintillator, a brightness retention rate, which is measured 24 hours after 38-minute irradiation with an X-ray to a total irradiation dose of 13 kGy at a distance of 40 mm from a radiation source, is 65% or higher; the Rockwell hardness is 30 HRM or higher; and the content of the resin is not less than 10% by weight.
    Type: Application
    Filed: September 16, 2021
    Publication date: January 6, 2022
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Takeshi Kuriwada, Takeshi Oomori, Tomoyuki Kurushima
  • Patent number: 8933394
    Abstract: A semiconductor device includes one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate. The semiconductor device further includes a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
  • Patent number: 8803161
    Abstract: A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 12, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
  • Publication number: 20130069082
    Abstract: A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.
    Type: Application
    Filed: February 23, 2011
    Publication date: March 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
  • Publication number: 20130033300
    Abstract: A semiconductor device includes one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate. The semiconductor device further includes a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode.
    Type: Application
    Filed: February 23, 2011
    Publication date: February 7, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroshi Okada, Takuya Sunada, Takeshi Oomori
  • Publication number: 20010044760
    Abstract: Provided are an orderer terminal 10, 11 performing ordering a product on the basis of product information and reception information, a reception computer 20 generating the reception information identifying an orderer in the order of reception on the basis of product information transmitted from the orderer terminal 10, 11, and transmitting it to the orderer terminal 10, 11, and an ordering computer 30 identifying the right/wrong of the reception information transmitted from the orderer terminal 10, 11 judged on the basis of the reception information received from the reception computer 20 that the reception succeeds, and starts order processing when the reception information is right reception information.
    Type: Application
    Filed: May 21, 2001
    Publication date: November 22, 2001
    Applicant: NEC Corporation
    Inventor: Takeshi Oomori