Abstract: An arithmetic processing apparatus computes a square root of a radicand and includes: a memory; and a processor coupled to the memory and configured to: determine a part of a bit string of a quotient; calculate a first partial remainder based on the bit string and a partial remainder by performing a first operation other than an exponentiation operation in a partial remainder operation; and calculate the partial remainder by performing a second operation that includes the exponentiation operation, using the first partial remainder and the bit string.

Abstract: An arithmetic processing device includes a processor that calculates a constant multiplication value by multiplying a constant value obtained by dividing a first value by a natural logarithm of 2 and a data value, separates the constant multiplication value into an integer portion and a fractional portion, calculates a fractional power value corresponding to a value of the fractional portion, calculates an integer power value corresponding to a value obtained by multiplying a value of the integer portion by a second value, calculates a power addition value by adding the fractional power value and the integer power value, calculate a power subtraction value by subtracting the integer power value from the fractional power value, and calculate a division value by dividing the power subtraction value by the power addition value as a result of an execution of an arithmetic operation of a hyperbolic tangent function with the data value.

Abstract: An arithmetic processing device includes a processor that calculates a constant multiplication value by multiplying a constant value obtained by dividing a first value by a natural logarithm of 2 and a data value, separates the constant multiplication value into an integer portion and a fractional portion, calculates a fractional power value corresponding to a value of the fractional portion, calculates an integer power value corresponding to a value obtained by multiplying a value of the integer portion by a second value, calculates a power addition value by adding the fractional power value and the integer power value, calculate a power subtraction value by subtracting the integer power value from the fractional power value, and calculate a division value by dividing the power subtraction value by the power addition value as a result of an execution of an arithmetic operation of a hyperbolic tangent function with the data value.

Abstract: A control apparatus controls the transmission of data from a transmission apparatus to a reception apparatus. The control apparatus includes: a first comparison unit that compares first information indicating a free space of a buffer included in the reception apparatus with second information indicating the size of data to be transmitted; a second comparison unit that compares the first information with third information obtained by adding a predetermined value to the second information; and a control unit that outputs a data output control signal based on the comparison result from the second comparison unit after the transmission of the data until the end of update of the first information, and outputs a data output control signal based on the comparison result from the first comparison unit after the update of the first information.