Abstract: According to one embodiment, there is provided an analysis method by a scanning transmission electron microscope including a dark field detector that detects dark field images by irradiating a sample with electron beams and detecting electron beams that are transmitted through or scattered from the sample, and an electron beam detector that detects electron diffraction images at radiation points of the electron beams among the electron beams that are transmitted through the sample or scattered from detecting the electron beams transmitted through a hollow portion of the dark field detector. The analysis method includes scanning a plurality of the radiation points set in an attention area by sequentially radiating electron beams at preset incidence angles, and performing detection of dark field images of the attention area and detection of NBD images at each of the plurality of radiation points at the same time.

Abstract: According to one embodiment, there is provided an analysis method by a scanning transmission electron microscope including a dark field detector that detects dark field images by irradiating a sample with electron beams and detecting electron beams that are transmitted through or scattered from the sample, and an electron beam detector that detects electron diffraction images at radiation points of the electron beams among the electron beams that are transmitted through the sample or scattered from detecting the electron beams transmitted through a hollow portion of the dark field detector. The analysis method includes scanning a plurality of the radiation points set in an attention area by sequentially radiating electron beams at preset incidence angles, and performing detection of dark field images of the attention area and detection of NBD images at each of the plurality of radiation points at the same time.

Abstract: On a transmission path connecting a first semiconductor integrated circuit that is started by a system management apparatus and a second semiconductor integrated circuit that is not started by the system management apparatus, when connection of the first semiconductor integrated circuit to the second semiconductor integrated circuit is detected, after being turned to a first signal state for detecting a valid lane, each lane on the transmission path is turned to a second signal state corresponding to each bit of initial setting code. In the second semiconductor integrated circuit, the first and second signal states are detected for each lane of the transmission path. Based on the detected signal state, after detecting the first signal state, the second signal state is detected and each bit value of the initial setting code is decoded. Based on the decoded initial setting code, an initialization process is executed.

Abstract: A relay device includes a first determining unit, a first sending unit, a receiving unit, a setting unit, a second determining unit, and a second sending unit. When the first determining unit determines that the relay device is a parent node, the first sending unit sends a set value stored in a storing unit to all the other relay devices to which the relay device is connected. When the first determining unit determines that the relay device is not the parent node, the receiving unit receives the set value. The setting unit sets the set value received by the receiving unit in the storing unit. When the second determining unit determines that the received set value has not been sent to the other relay devices, the second sending unit sends the received set value to the other relay devices to which the relay device is connected.

Abstract: A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.

Abstract: To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.

Abstract: A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.

Abstract: A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.

Abstract: A method of switching internal settings in an information processing apparatus including a plurality of processors, a crossbar switch connected to the plurality of processors and having a first routing table and a second routing table used for routing between the plurality of processors and an external apparatus, and a management unit managing the plurality of processors. The method includes performing, by the processors, data communication with the external apparatus using the first routing table, updating, by the management unit, configuration information in the second routing table when a configuration of the information processing apparatus is changed, instructing, by the management unit, any one of the processors to switch the updated second routing table and the first routing table, and switching, by the processor instructed by the management unit, a routing table to be used for the data communication from the first routing table to the updated second routing table.

Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

Abstract: A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.

Abstract: A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.

Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Abstract: A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.

Abstract: A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.

Abstract: A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.

Abstract: In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.

Abstract: A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.

Abstract: In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.

Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.