Patents by Inventor Takeshi Sampei

Takeshi Sampei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4766058
    Abstract: A photographic material comprising at least one blue sensitive silver halide emulsion layer is disclosed. The silver density of the emulsion layer is not less than 4.0.times.10.sup.-1 g/cm.sup.3 and the dry thickness of the layer is not more than 4.0 .mu.m. A core/shell type silver halide emulsion and a high-speed reaction type scavenger for the oxidation products of a developing agent are preferably used for the emulsion layer. The photographic material has a high sensitivity and provides an image having a superior sharpness and resolution.
    Type: Grant
    Filed: July 16, 1986
    Date of Patent: August 23, 1988
    Assignee: Konishiroku Photo Industry Co., Ltd.
    Inventors: Takeshi Sampei, Toshifumi Iijima, Yoshitaka Yamada, Hiroshi Shimazaki, Kenji Kumashiro, Yoshiharu Mochizuki, Syoji Matsuzaka, Hiroshi Kashiwagi
  • Patent number: 4512012
    Abstract: A time-switch circuit for use in a primary time switch (PTSW), a secondary time switch (STSW), and a space switch (SSW) of a digital time-division switching system is disclosed. The time switch comprises a plurality of memory circuits (MUC.sub.11 to MUC.sub.15, MUC.sub.21 to MUC.sub.25). Each memory circuit comprises a memory unit (MEM), an address buffer (AB) for a first address, an m-ary counter (T-CTR) for a second address, an address selector (AS) for selecting either the first or second address, an input data buffer (IB), and an output data buffer (OB). In a write cycle, input data from the input data buffer is written into the memory unit by either the first or second address signal, and in a read cycle, output data is read out of the memory unit by either the second or first address. Selection of the first and second addresses is performed by the address selector, which is controlled by an address-selection mode switch circuit (M.sub.0).
    Type: Grant
    Filed: February 10, 1983
    Date of Patent: April 16, 1985
    Assignee: Fujitsu Limited
    Inventors: Takeshi Sampei, Norio Miyahara, Tadanobu Nikaido, Hiroaki Sato, Keizo Aoyama