Patents by Inventor Takeshi Shichi

Takeshi Shichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8658508
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8629030
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8501585
    Abstract: To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a first semiconductor wafer in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a single crystal semiconductor layer used as a channel formation region of the transistor from the first semiconductor wafer and transferring the single crystal semiconductor layer to a second semiconductor wafer.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Shichi, Naoki Suzuki
  • Patent number: 8455331
    Abstract: To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a semiconductor substrate in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a semiconductor layer of the transistor from the semiconductor substrate and transferring the semiconductor layer to a supporting substrate that is a substrate having an insulating surface.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Shichi, Naoki Suzuki
  • Publication number: 20120164817
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Application
    Filed: March 5, 2012
    Publication date: June 28, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takeshi SHICHI, Junichi KOEZUKA, Hideto OHNUMA, Shunpei YAMAZAKI
  • Patent number: 8143134
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8048749
    Abstract: A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Atsuo Isobe, Motomu Kurata, Takeshi Shichi, Daisuke Ohgarane, Takashi Shingu
  • Publication number: 20100087044
    Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.
    Type: Application
    Filed: September 28, 2009
    Publication date: April 8, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
  • Publication number: 20090098674
    Abstract: To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a semiconductor substrate in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a semiconductor layer of the transistor from the semiconductor substrate and transferring the semiconductor layer to a supporting substrate that is a substrate having an insulating surface.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 16, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Takeshi SHICHI, Naoki SUZUKI
  • Publication number: 20090098690
    Abstract: To realize high 2 performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a first semiconductor wafer in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a single crystal semiconductor layer used as a channel formation region of the transistor from the first semiconductor wafer and transferring the single crystal semiconductor layer to a second semiconductor wafer.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Takeshi SHICHI, Naoki SUZUKI
  • Patent number: 7503975
    Abstract: In a crystalline silicon film fabricated by a related art method, the orientation planes of its crystal randomly exist and the orientation rate relative to a particular crystal orientation is low. A semiconductor material which contains silicon as its main component and 0.1-10 atomic % of germanium is used as a first layer, and an amorphous silicon film is used as a second layer. Laser light is irradiated to crystallize the amorphous semiconductor films, whereby a good semiconductor film is obtained. In addition, TFTs are fabricated by using such a semiconductor film.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: March 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
  • Publication number: 20090029514
    Abstract: A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).
    Type: Application
    Filed: July 23, 2008
    Publication date: January 29, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tomokazu YOKOI, Atsuo ISOBE, Motomu KURATA, Takeshi SHICHI, Daisuke OHGARANE, Takashi SHINGU
  • Patent number: 7449408
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a method for manufacturing a semiconductor device having a laminated structure by forming an interlayer insulating layer with an organic resin.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: November 11, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Muranaka, Ryoji Nomura, Takeshi Shichi, Tatsuya Arao, Masahiro Katayama
  • Patent number: 7368335
    Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 6, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
  • Patent number: 7307282
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Publication number: 20060246638
    Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.
    Type: Application
    Filed: April 25, 2006
    Publication date: November 2, 2006
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
  • Patent number: 7034337
    Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: April 25, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
  • Patent number: 6956235
    Abstract: The orientation of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is improved and a TFT formed from this crystalline semiconductor film is provided. In a semiconductor device whose TFT is formed from a semiconductor layer mainly containing silicon, the semiconductor layer has a channel formation region and an impurity region doped with an impurity of one type of conductivity.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: October 18, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo
  • Publication number: 20050164520
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a method for manufacturing a semiconductor device having a laminated structure by forming an interlayer insulating layer with an organic resin.
    Type: Application
    Filed: June 8, 2004
    Publication date: July 28, 2005
    Inventors: Koji Muranaka, Ryoji Nomura, Takeshi Shichi, Tatsuya Arao, Masahiro Katayama
  • Patent number: 6830994
    Abstract: The number of grains in active regions of devices can be made uniform by making the grains of crystalline semiconductor films, obtained by thermal crystallization using a metal element, smaller. The present invention is characterized in that a semiconductor film is exposed within an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma, and then thermal crystallization using a metal element is performed. The concentration of crystal nuclei1 generated is thus increased, making the grain size smaller, by performing these processes. Heat treatment may also be performed, of course, after exposing the semiconductor film, to which the metal element is added, to an atmosphere in which a gas, having as its main constituent one or a plurality of members from the group consisting of inert gas elements, nitrogen, and ammonia, is processed into a plasma.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: December 14, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Mitsuki, Takeshi Shichi, Shinji Maekawa, Hiroshi Shibata, Akiharu Miyanaga