Patents by Inventor Takeshi Shigeno

Takeshi Shigeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8607214
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: December 10, 2013
    Assignee: Hitachi Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Publication number: 20100011349
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Applicant: HITACHI, LTD.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Patent number: 7610581
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: October 27, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Publication number: 20050177648
    Abstract: In a data processing system which runs a plurality of operating systems, a channel device can be shared by the plurality of operating systems. In addition, a channel device which supports port multiplexing can also be shared by a plurality of operating systems. The channel device includes a plurality of IDs each indicating that the channel device is a medium for performing input/output processing, and an input/output processing controller for assigning one operating system to each of the IDs, and controlling a data transfer independently for each ID to control a plurality of data transfers. Further, in a channel device which has a plurality of ports, an input/output processing controller is provided for assigning an operating system to each of the ports, and transferring data independently for each port to control the plurality of ports.
    Type: Application
    Filed: January 3, 2005
    Publication date: August 11, 2005
    Inventors: Yoshihiro Toyohara, Tetsuhiro Goto, Megumu Hasegawa, Takeshi Shigeno
  • Patent number: 6247093
    Abstract: A data processing apparatus has a basic processing unit (BPU) 2, a channel processor (CHP) 10, message channel units (MCH) 11n, message channel receivers (MCHR) 6m connected respectively to the message channel units 11n, and a structured external storage device (SES) 6 which may be connected to a plurality of hosts via the message channel receivers 6m and which includes a cache memory 8 for accommodating data shared by the hosts. Before issuing a synchronous instruction, a program issues an instruction notifying in advance the inventive apparatus of the intended use of hardware resources. When the hardware resources are reserved by the notifying instruction, the apparatus guarantees the subsequent execution of the synchronous instruction. Because synchronous instructions are always carried out, the system overhead is lowered.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: June 12, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Shigeno, Takashi Morikawa
  • Patent number: 6144995
    Abstract: A data transfer method for a computer system in which a computer is logically divided into a plurality of logical processing units and a logical coupling unit. A correspondence between a start of physical addresses of a memory of each logical processing units in a memory of the computer is stored in advance. If a first logical processing unit issues a write command to the logical coupling unit by designating a logical address of data, the logical coupling unit stores an identifier and the logical address of the first logical processing unit. If a second logical processing unit issues a read command of the data, a physical address of data storage corresponding to the logical address of the first logical processing unit is calculated in accordance with the identifier and the logical address of the first logical processing unit and the address correspondence. The data is read by using the calculated physical address.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: November 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Yuzuru Maya, Akira Otsuji, Takeshi Shigeno