Abstract: In a liquid crystal drive controller formed as a semiconductor integrated circuit having therein a power source circuit including a boosting circuit and driving a source line and a gate line of a TFT liquid crystal panel, the number of external capacitive elements and the number of external terminals for connecting the external capacitive elements are reduced, thereby reducing the size and cost of the chip and an electronic device on which the chip is mounted. As a boosting circuit for generating a voltage for driving a source line of the TFT liquid crystal panel in the liquid crystal controller having therein the power source including the boosting circuit, a boosting circuit having an external capacitive element is used. On the other hand, as a boosting circuit for generating a voltage for driving a gate line, a charge pump having a built-in (on-chip) capacitive element is used.

Abstract: A coupler/isolator alternatively couples and isolates unit amplifiers of a multiple stage chopper amplifier to shift gradually and slightly reset timing and amplification timing of the chopper amplifiers. In this way, a first-stage chopper amplifier to an n-th timing of the chopper amplifiers. In this way, a first-stage chopper amplifier to an n-th stage chopper amplifier are sequentially reset. The first-stage chopper amplifier to the n-th stage chopper amplifier are sequentially operated to amplify, in a pipeline format, a differential voltage between a signal voltage input to a signal voltage input terminal and a reference voltage input to a reference voltage input terminal, and supply the amplified differential voltage to a next-stage circuit.

Abstract: First-stage coupler/isolator to (n−1-th stage coupler/isolator repeat isolation, coupling, isolation and so on between unit amplifiers from the first-stage chopper amplifier to n-th stage chopper amplifier to shift gradually and slightly a reset timing and an amplification timing of these chopper amplifiers. In this way, the first-stage chopper amplifier to the n-th stage chopper amplifier are sequentially reset, and the first-stage chopper amplifier to the n-th stage chopper amplifier are sequentially operated to amplify in a pipeline format a differential voltage between a signal voltage input to a signal voltage input terminal and a reference voltage input to a reference voltage input terminal, and supply the amplified differential voltage to a next-stage circuit.

Abstract: An object is to obtain an A/D converter with improved A/D conversion accuracy. The resistor elements (R) and (R) are connected through wiring (L10) (2×L11, L12, 2×L13) mostly with two resistor elements left therebetween. For example, the resistor elements (R1) and (R2) are connected through the partial wiring (L11) and (L13) extended to the left in the diagram, and the resistor elements (R3) and (R4) are connected through the partial wiring (L11) and (L13) extended to the right in the diagram. Thus all of the wiring (L10) connecting electrically adjacent resistor elements (R) and (R) are formed of a combination of partial wiring {2×L11, L12, 2×L13}.

Abstract: In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).

Abstract: An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.