Abstract: A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

Abstract: A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

Abstract: A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

Abstract: A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

Abstract: A hemostasis tool is provided for stopping bleeding by absorbing blood from the wound and having blood diffusion and absorption abilities, which includes a lamination comprising a water-permeable inner material on a wound side, a water-impermeable outer material on a side departing from the wound side, a pulp-cotton laminated body between the inner and outer materials, a crust between the pulp-cotton laminated body and the water-impermeable outer material for diffusing the blood that has passed through the water-permeable inner material and the pulp-cotton laminated body, and a polymer for absorbing the blood diffused by the crust. Instead of the pulp-cotton laminated body, a synthesis fiber laminated body can be utilized in the hemostasis tool having a laminated structure.

Abstract: A hemostasis tool is provided for stopping bleeding by absorbing blood from the wound and having blood diffusion and absorption abilities, which includes a lamination comprising a water-permeable inner material on a wound side, a water-impermeable outer material on a side departing from the wound side, a pulp-cotton laminated body between the inner and outer materials, a crust between the pulp-cotton laminated body and the water-impermeable outer material for diffusing the blood that has passed through the water-permeable inner material and the pulp-cotton laminated body, and a polymer for absorbing the blood diffused by the crust. Instead of the pulp-cotton laminated body, a synthesis fiber laminated body can be utilized in the hemostasis tool having a laminated structure.

Abstract: A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n?2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

Abstract: A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n?2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

Abstract: The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other.

Abstract: The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other.

Abstract: The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other.

Abstract: In a MODEM having modulation and demodulation circuits and a circuit for controlling the modulation and demodulation, a modulator-demodulator apparatus includes a register for accepting a macro-instruction from an external source; a circuit for interpreting and executing the macro-instruction; and a circuit for outputting a response to the macro-instruction, whereby the MODEM is controlled in response to the macro-instruction accepted from the outside source. The modulator-demodulator apparatus is suitably integrated over a single semiconductor substrate.